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A charge-based continuous model for small-geometry graded-channel SOI MOSFET's
(2005-09-07) Michelly De Souza; Marcelo Antonio Pavanello
In this work a continuous model for analog simulation of short-channel Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFET is presented. Effects of channel length modulation and velocity saturation have been included in the model formulation, which is based on the series combination of two conventional SOI nMOSFETs, each one representing one of the regions of GC SOI MOSFET channel and its characteristics. Experimental results and numerical bidimensional simulations are used to validate the model with excellent agreement in both cases.
A fully analytical continuous model for graded-channel SOI MOSFET for analog applications
(2004-09-11) Michelly De Souza; Marcelo Antonio Pavanello; INIGUEZ, B.; FLANDRE, D.
In this work an analytical model of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs is proposed for analog applications. The model is based on a series association of two conventional SOI nMOSFETs each representing one part of the GC SOI nMOSFET channel. From this assumption, we propose a current model that considers the GC SOI MOSFET as a conventional SOI transistor, represented by one part of the channel only, in which the drain voltage is modulated by the remaining part. The proposed model has been verified through the comparison between its results and experimental measurements, presenting a good agreement. Some important characteristics for analog circuits, such as transconductance and Early voltage, are compared between the model results and experimental curves.
A kernel maximum uncertainty discriminant analysis and its application to face recognition
(2009-02-05) Carlos E. Thomaz; GIRALDI, G. A.
In this paper, we extend the Maximum uncertainty Linear Discriminant Analysis (MLDA), proposed recently for limited sample size problems, to its kernel version. The new Kernel Maximum uncertainty Discriminant Analysis (KMDA) is a two-stage method composed of Kernel Principal Component Analysis (KPCA) followed by the standard MLDA. In order to evaluate its effectiveness, experiments on face recognition using the well-known ORL and FERET face databases were carried out and compared with other existing kernel discriminant methods, such as Generalized Discriminant Analysis (GDA) and Regularized Kernel Discriminant Analysis (RKDA). The classification results indicate that KMDA performs as well as GDA and RKDA, with the advantage of being a straightforward stabilization approach for the within-class scatter matrix that uses higher-order features for further classification improvements.
A multivariate statistical analysis of muscular biopotencial for human arm movement characterization
(2009-01-14) SILVA, G. A. DA; Castro, M.C.F.; Carlos E. Thomaz
Pattern recognition of electromyographic signals consists of a hard task due to the high dimensionality of the data and noise presence on the acquired signals. This work intends to study the data set as a multivariate pattern recognition problem by applying linear transformations to reduce the data dimensionality. Five volunteers contributed in a previous experiment that acquired the myoelectrical signals using surface electrodes. Attempts to analyse the groups of acquired data by means of descriptive statistics have shown to be inconclusive. This works shows that the use of multivariate statistical techniques such as Principal Components Analysis (PCA) and Maximum uncertainty Linear Discriminant Analysis (MLDA) to characterize the: acquired set of signals through low dimensional scatter plots provides a new understanding of the data spread, making easier its analysis. Considering the arm horizontal movement and the acquired set of data used in this research, a multivariate linear separation between the patterns of interest quantified by the distance of Bhattacharyya suggests that it's possible not only to characterize the angular joint position, but also to confirm that different movements recruit similar amounts of energy to be executed.
A simple method to model nonrectangular-gate layout in SOI MOSFETs
(2005-09-07) Renato Giacomini; MARTINO, J. A.
A simple method to obtain an analytical current model for nonrectangulargate layout in SOI MOSFETs is presented, based on partition of the original layout into trapezoidal parts, and modeling these trapezoids by a closed form expression. A generic shape factor is defined for comparison between devices of different shapes in the same technology. Three-dimensional simulation and some experimental results were carried out to verify the method accurateness. The obtained expression showed good agreement both to simulation and experimental results. The method can be applied to a wide range of gate layout shapes.
A study of total series resistance and effective channel length comparing SOI nMOSFET and GC SOI nMOSFET in saturation region
(2005-09-07) ALMEIDA, G. F. DE; MARTINO, J. A.
This work presents a study of total series resistance (Rs) and effective channel length (Leff) comparing conventional SOI and GC SOI nMOSFETs in saturation region. The GC and conventional SOI devices have different behaviors due to the structural differences. The lower doped region of the GC devices has fundamental influence in RS and Leff extraction, i.e., it suggests that its intrinsic resistance value is added to the series resistance parameter and not to the channel one. Such behavior also influences the extraction of Leff, as the applied method shows.
An improved model for the triangular SOI misalignment test structure
(2004-09-07) Renato Giacomini; MARINO, J. A.
The triangular misalignment test structure is an arrangement of MOS transistors to calculate the poly and source/drain diffusion misalignment as a function of drain current differences. Although these structures have non-rectangular shapes, which may be detrimental for the design, the advantage of measuring currents instead of voltage differences make them very useful. This work presents a new analytic misalignment error model for thin-film, fully depleted SOI technology, using non rectangular devices. Three-dimensional numerical simulation is used as a reference for models comparison and verification. These simulation results show that the proposed analytical model presents an improved performance compared to those available in the literature.
Analysis of deep submicrometer bulk and fully depleted SOI nmosfet analog operation at cryogenic temperatures
(2005-05-20) Marcelo Antonio Pavanello; Joao Antonio Martino; SIMOEN, E.; CLAEYS, C.
The increased demand for mixed mode digital-analog circuits is playing an important role nowadays. As the temperature of operation is decreased well-known improvements in the digital characteristics as reduction of the subthreshold slope and increased carrier mobility are obtained leading to better performance characteristics without scaling the dimensions. In this work, the impact of the temperature reduction on the analog characteristics of deep submicrometer bulk and fully depleted SOI nMOSFETs is compared. It is shown that the Early voltage does not vary appreciably with temperature and the intrinsic gain is substantially improved in bulk deep submicrometer transistors. On the other hand, deep submicrometer fully depleted SOI can operate at reduced bias current to bias the same load in base-band applications.
Analysis of harmonic distortion in graded-channel SOI MOSFETS at high temperatures
(2004-09-11) Marcelo Antonio Pavanello; CERDEIRA, A.; MARTINO, J. A.; ALEMAN, M. A.; FLANDRE, D.
An evaluation of the harmonic distortion in conventional and graded-channel SOI MOSFETs is performed from room temperature up to 423 K. The total harmonic distortion and third order harmonic distortion have been adopted as figures of merit. It is shown that the total harmonic distortion decreases as the length of the lightly doped region is increased in GC transistors, due to reduction of the effective voltage amplitude that is applied on the conventionally doped part of the channel. On the other hand, the third order harmonic distortion increases with the length of lightly doped region. The temperature increase tends to reduce the total harmonic distortion and the third order harmonic.
Analysis of self-heating effect in graded-channel silicon-on-insulator nMOSFETs
(2007-08-28) COSTA, S. E. DE S.; Marcelo Antonio Pavanello; Joao Antonio Martino
This paper presents a Self-Heating (SH) analysis using conventional Silicon-On-Insulator (SOI) in comparison to Graded-Channel (GC) SOI nMOSFETs devices. The analysis is performed comparing devices with the same mask channel length and with the same effective channel length. Two-dimensional numerical simulations are performed in both studies considering the lattice heating. The models and the thermal conductive constant used in these simulations are also presented. It is demonstrated that GC devices with the same mask channel length presents similar occurrence of SH independently of the length of lightly doped region despite the larger drain current. On the other hand, for similar effective channel length, the SH is less pronounced in GC transistors as the mask channel length has to be increased in order to compensate the current difference. © 2006 The Electrochemical Society.
Analysis of silicon thickness reduction on analog parameters of GC GAA SOI transistors operating up to 300°C
(2006-09-01) SANTOS, C. D. G. DOS; Marcelo Antonio Pavanello; Joao Antonio Martino
This paper analyzes the impact of silicon film thickness reduction in some analog parameters of Gate-All-Around (GAA) transistors using the graded-channel (GC) architecture. The study was done at high temperatures (up to 300°C) through two-dimensional simulations. As the silicon film is reduced an improvement on the Early voltage was observed. However, for GC GAA devices this improvement is more pronounced at room temperature than at high temperatures. The output swing voltage (Vos) was also studied and it decreases while reducing the silicon thickness. Regarding the GC GAA the Vos is larger than conventional GAA in 50 nm thick transistors. © 2006 The Electrochemical Society.
Analysis of the linear kink effect in partially depleted SOI nMOSFET's
(2005-09-07) AGOPIAN, P. G.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.
In this work, the occurrence of the linear kink effect (LKE) in PD SOI nMOSFETs is investigated experimentally and by two-dimensional simulations. The experimental dependence of the LKE on the drain voltage and the channel length is reported, showing a reduction of the second peak in the transconductance when the transistor channel length decrease. By two-dimensional numerical simulations, the impact of various parameters on this second peak has been studied, namely, the gate current level, the carrier lifetime, the increase of the body potential and the threshold voltage variation.
Application of the symmetric doped double-gate model in circuit simulation containing double-gate graded-channel transistors
(2010-09-05) CONTRERAS, E.; CERDEIRA, A.; ALVARADO, J.; Marcelo Antonio Pavanello
The development of models to simulate circuits containing new devices is an important task to allow the introduction of these devices in practical applications. In this paper we show the advantages of using the recently developed Symmetric Doped Double-Gate Model as already introduced in SmartSpice simulator, for modeling circuits containing Double-Gate Graded-Channel (GC) transistors. In this case there is no need to use two different models to represent the graded-channel device, as has been done up to now. Current-mirror circuits using GC devices have been simulated and the results were validated comparing them with those obtained using the MIXED-MODE module of two-dimensional numerical ATLAS simulator of the GC devices.
Behavior of Graded Channel SOI Gate-All-Around nMOSFET devices at high temperatures
(2004-09-11) SANTOS, C. D. G. DOS; Marcelo Antonio Pavanello; MARTINO, J. A.; FLANDRE, D.; RASKIN, J.-P.
This paper presents the behavior of Graded Channel SOI Gate-All-Around (GAA) nMOSFET at high temperatures in the range of 27°C to 300°C. Threshold voltage, subthreshold slope, maximum transconductance, zero temperature coefficient and Early voltage were investigated through three-dimensional simulations and electrical characterization. It was verified that when temperature increases, threshold voltage decreases, subthreshold slope increases and did not suffer any degradation with the LLD/L ratio increase. The maximum transconductance decreases when temperature increases, and increases for larger LLD/L ratios, and Early voltage decreases almost linearly with temperature increase. The results show the excellent behavior of GC SOI GAA nMOSFET at high temperatures compared to conventional SOI GAA devices.
Channel length reduction influence on harmonic distortion of graded-channel gate-all-around devices
(2006-09-01) Rodrigo Doria; Marcelo Antonio Pavanello; CERDEIRA, A.; RASKIN, J. P.; FLANDRE, D.
This work compares the linearity of conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices for analog operation as in an amplifier when the channel length is scaled. The study has been performed through two-dimensional process and device simulations. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated. When taking into account similar bias the performance of GC GAA transistors remains better than the uniformly doped GAA for any channel length. Although scaling the devices tends to degrade the harmonic distortion, significant results were obtained for the GC configuration measured as an improvement of more than 15 dB in total harmonic distortion-to-gain ratio operating in the same region with channel length of 1uμm and with lightly doped region length of 0.3 μm. © 2006 The Electrochemical Society.
Charge-based continuous explicit equations for the transconductance and output conductance of submicron graded-channel SOI mosfet's
(2006-09-01) Michelly De Souza; Marcelo Antonio Pavanello
This paper presents charge-based continuous explicit equations for the transconductance and output conductance of submicron Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFET. Short-channel effects like channel length modulation, velocity saturation and drain-induced barrier lowering have been considered in the proposed expressions. Experimental results were used to test the equations by comparing not only the transconductance and the output conductance, but also the Early voltage and the open-loop voltage gain, showing a good agreement as well as smooth transitions between the different regions of operation, validating the proposed equations. © 2006 The Electrochemical Society.
Comparison between bulk and floating body partially depleted SOI nMOSFETS for high frequency analog applications operating from 300 K down to 95 K
(2005-09-07) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.
A comparison between deep-submicrometer bulk and floating-body partially depleted (PD) SOI nMOSFET operation for high frequency analog applications is performed from room temperature down to 95 K. The transistor intrinsic gain, cutoff frequency and bias current are used as figures of merit for this comparison. It is demonstrated that bulk transistors can have larger intrinsic gain at any temperature of operation due to their larger Early voltage. On the other hand, the cutoff frequency is improved in PD SOI without halo due to the larger carrier mobility and velocity saturation. Also PD SOI without halo reaches a frequency of 13 GHz at 95 K, whereas bulk and PD SOI with halo reach 11 GHz for the same load capacitance of 100 fF.
Digital signal processing with MatLab and DSP Kits
(2004-08-04) MELO, M. A. A. DE; Fabrizio Leonardi; LA NEVE, A.
A methodology, based on progressive steps, has been developed, so that the students be prepared to design and implement typical industrial projects, such as digital filters, voice processing algorithms, and others, and also be able to correlate this knowledge with other disciplines. They start with an analog system, described by a differential equation, from which a generic discrete equation is generated. The projects are initially simulated with MatLab, and they are then implemented with DSP TMS320C31. The projects are always based on a fundamental equation of differences, representing a digital filter: this is very important for the study of digital processing concepts, such as system stability, system order, computational complexity, and so on. The simulation helps the students to understand a system digitalization process. The results obtained with the students in the course show the efficiency of this methodology. ©2004 IEEE.
Distributed DSP processing for multivariable state equations
(2004-08-04) Fabrizio Leonardi; MELO, M. A. A. DE; LA NEVE, A.
This work deals with the synthesis of a multivariable digital controller when its hardware must be decentralized. Thus, it can be used as a way to implement dynamic equations in state space for hardware with limited inputs and outputs. The method consists in breaking equations, while keeping the overall transfer matrix, resulting in a distributed implementation. The solution has a modular structure for an arbitrary number of inputs and outputs. It is shown a way to perform the synthesis by using the same dynamic matrix. As a consequence the computational demand could not be severely reduced when compared with a centralized controller. Nevertheless, the synthesis is actually distributed since each part is implemented with a smaller number of inputs and outputs. A multivariable controller of an inverted pendulum is used as an example. ©2004 IEEE.
Early voltage behavior in circular gate SOI nMOSFET using 0.13 μm partially-depleted SOI CMOS technology
(2006-09-01) Salvador Gimenez; FERREIRA, R. M. G.; Joao Antonio Martino
This paper studies the Early voltage behavior in circular gate partially-depleted SOI nMOSFET. The drain/source asymmetric effects are considered in terms of drain current as a function of the gate and drain voltages. Drain current comparisons with rectangular gate partially-depleted SOI nMOSFET are performed, regarding the same effective channel length and width. Experimental results and three-dimensional simulations are used to qualify the results. © 2006 The Electrochemical Society.

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