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A charge-based continuous model for small-geometry graded-channel SOI MOSFET's
(2005-09-07) Michelly De Souza; Marcelo Antonio Pavanello
In this work a continuous model for analog simulation of short-channel Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFET is presented. Effects of channel length modulation and velocity saturation have been included in the model formulation, which is based on the series combination of two conventional SOI nMOSFETs, each one representing one of the regions of GC SOI MOSFET channel and its characteristics. Experimental results and numerical bidimensional simulations are used to validate the model with excellent agreement in both cases.
A framework of intentional characters for simulation of social behavior
(2010-07-12) DA COSTA, L.C.; CLUA, E.W.; GIRALDI, G. A.; BERNARDINI, F. C.; Reinaldo Bianchi; SCHULZE, B.; MONTENEGRO, A. A.
Realism is thriving today in many types of media, particularly in video games, where the polygon count continues growing up. However, this realism pushes up the necessity of a real behavior of the virtual actors, in order to follow the credibility of the characters. We present an approach for crowd simulation that works adaptively to situations that occur in virtual atmosphere. Our approach allows that a realistic character adapts his behavior and actions with the information noticed from the atmosphere which it is close to. For this work, the execution atmosphere will be a simulation of a real catastrophic atmosphere, such as as flooding and collapses.
A fully analytical continuous model for graded-channel SOI MOSFET for analog applications
(2004-09-11) Michelly De Souza; Marcelo Antonio Pavanello; INIGUEZ, B.; FLANDRE, D.
In this work an analytical model of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs is proposed for analog applications. The model is based on a series association of two conventional SOI nMOSFETs each representing one part of the GC SOI nMOSFET channel. From this assumption, we propose a current model that considers the GC SOI MOSFET as a conventional SOI transistor, represented by one part of the channel only, in which the drain voltage is modulated by the remaining part. The proposed model has been verified through the comparison between its results and experimental measurements, presenting a good agreement. Some important characteristics for analog circuits, such as transconductance and Early voltage, are compared between the model results and experimental curves.
A kernel maximum uncertainty discriminant analysis and its application to face recognition
(2009-02-05) Carlos E. Thomaz; GIRALDI, G. A.
In this paper, we extend the Maximum uncertainty Linear Discriminant Analysis (MLDA), proposed recently for limited sample size problems, to its kernel version. The new Kernel Maximum uncertainty Discriminant Analysis (KMDA) is a two-stage method composed of Kernel Principal Component Analysis (KPCA) followed by the standard MLDA. In order to evaluate its effectiveness, experiments on face recognition using the well-known ORL and FERET face databases were carried out and compared with other existing kernel discriminant methods, such as Generalized Discriminant Analysis (GDA) and Regularized Kernel Discriminant Analysis (RKDA). The classification results indicate that KMDA performs as well as GDA and RKDA, with the advantage of being a straightforward stabilization approach for the within-class scatter matrix that uses higher-order features for further classification improvements.
A multivariate statistical analysis of muscular biopotencial for human arm movement characterization
(2009-01-14) SILVA, G. A. DA; Castro, M.C.F.; Carlos E. Thomaz
Pattern recognition of electromyographic signals consists of a hard task due to the high dimensionality of the data and noise presence on the acquired signals. This work intends to study the data set as a multivariate pattern recognition problem by applying linear transformations to reduce the data dimensionality. Five volunteers contributed in a previous experiment that acquired the myoelectrical signals using surface electrodes. Attempts to analyse the groups of acquired data by means of descriptive statistics have shown to be inconclusive. This works shows that the use of multivariate statistical techniques such as Principal Components Analysis (PCA) and Maximum uncertainty Linear Discriminant Analysis (MLDA) to characterize the: acquired set of signals through low dimensional scatter plots provides a new understanding of the data spread, making easier its analysis. Considering the arm horizontal movement and the acquired set of data used in this research, a multivariate linear separation between the patterns of interest quantified by the distance of Bhattacharyya suggests that it's possible not only to characterize the angular joint position, but also to confirm that different movements recruit similar amounts of energy to be executed.
A simple method to model nonrectangular-gate layout in SOI MOSFETs
(2005-09-07) Renato Giacomini; MARTINO, J. A.
A simple method to obtain an analytical current model for nonrectangulargate layout in SOI MOSFETs is presented, based on partition of the original layout into trapezoidal parts, and modeling these trapezoids by a closed form expression. A generic shape factor is defined for comparison between devices of different shapes in the same technology. Three-dimensional simulation and some experimental results were carried out to verify the method accurateness. The obtained expression showed good agreement both to simulation and experimental results. The method can be applied to a wide range of gate layout shapes.
A study of total series resistance and effective channel length comparing SOI nMOSFET and GC SOI nMOSFET in saturation region
(2005-09-07) ALMEIDA, G. F. DE; MARTINO, J. A.
This work presents a study of total series resistance (Rs) and effective channel length (Leff) comparing conventional SOI and GC SOI nMOSFETs in saturation region. The GC and conventional SOI devices have different behaviors due to the structural differences. The lower doped region of the GC devices has fundamental influence in RS and Leff extraction, i.e., it suggests that its intrinsic resistance value is added to the series resistance parameter and not to the channel one. Such behavior also influences the extraction of Leff, as the applied method shows.
A Study on Efficient Reinforcement Learning Through Knowledge Transfer
(2022-10-05) GLATT, R.; DA SILVA, F. L.; Reinaldo Bianchi; COSTA, A. H. R.
© 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.Although Reinforcement Learning (RL) algorithms have made impressive progress in learning complex tasks over the past years, there are still prevailing short-comings and challenges. Specifically, the sample-inefficiency and limited adaptation across tasks often make classic RL techniques impractical for real-world applications despite the gained representational power when combining deep neural networks with RL, known as Deep Reinforcement Learning (DRL). Recently, a number of approaches to address those issues have emerged. Many of those solutions are based on smart DRL architectures that enhance single task algorithms with the capability to share knowledge between agents and across tasks by introducing Transfer Learning (TL) capabilities. This survey addresses strategies of knowledge transfer from simple parameter sharing to privacy preserving federated learning and aims at providing a general overview of the field of TL in the DRL domain, establishes a classification framework, and briefly describes representative works in the area.
An improved model for the triangular SOI misalignment test structure
(2004-09-07) Renato Giacomini; MARINO, J. A.
The triangular misalignment test structure is an arrangement of MOS transistors to calculate the poly and source/drain diffusion misalignment as a function of drain current differences. Although these structures have non-rectangular shapes, which may be detrimental for the design, the advantage of measuring currents instead of voltage differences make them very useful. This work presents a new analytic misalignment error model for thin-film, fully depleted SOI technology, using non rectangular devices. Three-dimensional numerical simulation is used as a reference for models comparison and verification. These simulation results show that the proposed analytical model presents an improved performance compared to those available in the literature.
An investigation of actions, change and space
(2013-07-10) Paulo Santos; CABALAR, P.
This work investigates the spatial knowledge and automated solution of a domain composed of non-trivial objects such as strings and holed objects. Copyright © 2013, Association for the Advancement of Artificial Intelligence. All rights reserved.
An investigation of actions, change, space within a hole-loop dichotomy
(2013-05-27) Paulo Santos; CABALAR, P.
© COMMONSENSE 2013 - 11th International Symposium on Logical Formalizations of Commonsense Reasoning. All rights reserved.This work investigates the spatial knowledge of a domaincomposed of non-trivial objects such as strings and holed objects. To this aim, we consider the formalisation of puzzlelike examples as the starting point for the development ofKnowledge Representation systems. The present paper concentrates on the representation of "loops" (or loop-like regions) that can be formed by a flexible string, and that mayplay an essential part in the solution of physical problems involving strings.
Analog operation temperature dependence of nMOS junctionless transistors focusing on harmonic distortion
(2011-09-05) Rodrigo Doria; Marcelo Antonio Pavanello; TREVISOLI, R. D.; Michelly De Souza; LEE, C.-W.; FERAIN, I.; AKHAVAN, N. D.; YAN, R.; RAZAVI, P.; YU, R.; FRANTI, A.; COLINGE, J-P.
This paper performs a comparative study of the analog performance of Junctionless Nanowire Transistors (JNTs) and classical Trigate inversion mode (IM) devices focusing on the harmonic distortion. The study has been carried out in the temperature range of 223 K up to 473 K. The non-linearity or harmonic distortion (HD) has been evaluated in terms of the total and the third order distortions (THD and HD3, respectively) at a fixed input bias and at a targeted output swing. Several parameters important for the HD evaluation have also been observed such as the transconductance to the drain current ratio (gm/IDS), the Early voltage (VEA) and the intrinsic voltage gain (AV). Trigate devices showed maximum AV around room temperature whereas in JNTs the intrinsic voltage gain increases with the temperature. Due to the different AV characteristics, Junctionless transistors present improved HD at higher temperatures whereas inversion mode Trigate devices show better HD properties at room temperature.When both devices are compared, Junctionless transistors present better THD and HD3 with respect to the IM Trigate devices.
Analysis of deep submicrometer bulk and fully depleted SOI nmosfet analog operation at cryogenic temperatures
(2005-05-20) Marcelo Antonio Pavanello; Joao Antonio Martino; SIMOEN, E.; CLAEYS, C.
The increased demand for mixed mode digital-analog circuits is playing an important role nowadays. As the temperature of operation is decreased well-known improvements in the digital characteristics as reduction of the subthreshold slope and increased carrier mobility are obtained leading to better performance characteristics without scaling the dimensions. In this work, the impact of the temperature reduction on the analog characteristics of deep submicrometer bulk and fully depleted SOI nMOSFETs is compared. It is shown that the Early voltage does not vary appreciably with temperature and the intrinsic gain is substantially improved in bulk deep submicrometer transistors. On the other hand, deep submicrometer fully depleted SOI can operate at reduced bias current to bias the same load in base-band applications.
Analysis of harmonic distortion in graded-channel SOI MOSFETS at high temperatures
(2004-09-11) Marcelo Antonio Pavanello; CERDEIRA, A.; MARTINO, J. A.; ALEMAN, M. A.; FLANDRE, D.
An evaluation of the harmonic distortion in conventional and graded-channel SOI MOSFETs is performed from room temperature up to 423 K. The total harmonic distortion and third order harmonic distortion have been adopted as figures of merit. It is shown that the total harmonic distortion decreases as the length of the lightly doped region is increased in GC transistors, due to reduction of the effective voltage amplitude that is applied on the conventionally doped part of the channel. On the other hand, the third order harmonic distortion increases with the length of lightly doped region. The temperature increase tends to reduce the total harmonic distortion and the third order harmonic.
Analysis of self-heating effect in graded-channel silicon-on-insulator nMOSFETs
(2007-08-28) COSTA, S. E. DE S.; Marcelo Antonio Pavanello; Joao Antonio Martino
This paper presents a Self-Heating (SH) analysis using conventional Silicon-On-Insulator (SOI) in comparison to Graded-Channel (GC) SOI nMOSFETs devices. The analysis is performed comparing devices with the same mask channel length and with the same effective channel length. Two-dimensional numerical simulations are performed in both studies considering the lattice heating. The models and the thermal conductive constant used in these simulations are also presented. It is demonstrated that GC devices with the same mask channel length presents similar occurrence of SH independently of the length of lightly doped region despite the larger drain current. On the other hand, for similar effective channel length, the SH is less pronounced in GC transistors as the mask channel length has to be increased in order to compensate the current difference. © 2006 The Electrochemical Society.
Analysis of silicon thickness reduction on analog parameters of GC GAA SOI transistors operating up to 300°C
(2006-09-01) SANTOS, C. D. G. DOS; Marcelo Antonio Pavanello; Joao Antonio Martino
This paper analyzes the impact of silicon film thickness reduction in some analog parameters of Gate-All-Around (GAA) transistors using the graded-channel (GC) architecture. The study was done at high temperatures (up to 300°C) through two-dimensional simulations. As the silicon film is reduced an improvement on the Early voltage was observed. However, for GC GAA devices this improvement is more pronounced at room temperature than at high temperatures. The output swing voltage (Vos) was also studied and it decreases while reducing the silicon thickness. Regarding the GC GAA the Vos is larger than conventional GAA in 50 nm thick transistors. © 2006 The Electrochemical Society.
Analysis of the linear kink effect in partially depleted SOI nMOSFET's
(2005-09-07) AGOPIAN, P. G.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.
In this work, the occurrence of the linear kink effect (LKE) in PD SOI nMOSFETs is investigated experimentally and by two-dimensional simulations. The experimental dependence of the LKE on the drain voltage and the channel length is reported, showing a reduction of the second peak in the transconductance when the transistor channel length decrease. By two-dimensional numerical simulations, the impact of various parameters on this second peak has been studied, namely, the gate current level, the carrier lifetime, the increase of the body potential and the threshold voltage variation.
Application of the symmetric doped double-gate model in circuit simulation containing double-gate graded-channel transistors
(2010-09-05) CONTRERAS, E.; CERDEIRA, A.; ALVARADO, J.; Marcelo Antonio Pavanello
The development of models to simulate circuits containing new devices is an important task to allow the introduction of these devices in practical applications. In this paper we show the advantages of using the recently developed Symmetric Doped Double-Gate Model as already introduced in SmartSpice simulator, for modeling circuits containing Double-Gate Graded-Channel (GC) transistors. In this case there is no need to use two different models to represent the graded-channel device, as has been done up to now. Current-mirror circuits using GC devices have been simulated and the results were validated comparing them with those obtained using the MIXED-MODE module of two-dimensional numerical ATLAS simulator of the GC devices.
Aspects of risk of management in brazilian microgravity experiments: A case of study
(2014-10-03) LA NEVE, A.; CORRÊA, F. A.
Copyright © 2014 by the International Astronautical Federation. All rights reserved.Learning is a process strengthened by the praxis. The subject of the present article is to verify possible methodologies to mitigate risks in aerospace projects regarding such specific cases as new developments for future microgravity missions at Centro Universitário da FEI (FEI). The base of this study is the knowledge and experience acquired in projects in some microgravity missions in which FEI participated. FEI has been present right from the beginning of the Microgravity Program of the Brazilian Space Agency (AEB) in 2002 (CUMÃ Mission), developing microgravity experiments for national sounding rockets and the International Space Station (ISS). As a matter of fact, its involvement in the aerospace field is previous to the AEB Microgravity Program, and it started with the Space Shuttle STS-95 (Discovery mission, 1998), and soon after that with the sounding rocket missions São Marcos (1999) and Lençóis Maranhenses (2000). From mission to mission different scenarios appeared to the project management, popping up new barriers to overcome and bringing back old ones to the present: a set of occurrences in a comprehensive amount of uncertainties that face the manager skills to deal with. This paper intend to suggest some techniques to increase the success rate by implementing a risk management project with the evaluation of possible methodologies for risk mitigation projects, proposing recommendations related to the management of aerospace projects based primarily on theory, and then on known and successful practices adopted in projects already completed. A fundamental step for the risk comprehension is to identify the sources of uncertainties and deleterious consequences, or, in other words, the risk factors. The identification of common risk factors is investigated in bibliography, by surveys and by the use of a DELPHY methodology in order to validate the factors identified as significant risk sources and their root causes, including, in addition, the point of view of some other expert managers. This article is a particular case study of a broader survey that is being elaborated in the dissertation one of the authors', at the National Institute for Space Research, at São José dos Campos, Brazil. ia.
Behavior of Graded Channel SOI Gate-All-Around nMOSFET devices at high temperatures
(2004-09-11) SANTOS, C. D. G. DOS; Marcelo Antonio Pavanello; MARTINO, J. A.; FLANDRE, D.; RASKIN, J.-P.
This paper presents the behavior of Graded Channel SOI Gate-All-Around (GAA) nMOSFET at high temperatures in the range of 27°C to 300°C. Threshold voltage, subthreshold slope, maximum transconductance, zero temperature coefficient and Early voltage were investigated through three-dimensional simulations and electrical characterization. It was verified that when temperature increases, threshold voltage decreases, subthreshold slope increases and did not suffer any degradation with the LLD/L ratio increase. The maximum transconductance decreases when temperature increases, and increases for larger LLD/L ratios, and Early voltage decreases almost linearly with temperature increase. The results show the excellent behavior of GC SOI GAA nMOSFET at high temperatures compared to conventional SOI GAA devices.

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