Browsing by Author CASSÉ, MIKAËL
Showing results 1 to 6 of 6
| Issue Date | Title | Author(s) |
| 2018 | Electrical characterization of vertically stacked p-FET SOI nanowires | CARDOSO PAZ, BRUNA; CASSÉ, MIKAËL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; ANTONIO PAVANELLO, MARCELO |
| 2017 | Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K | PAZ, Bruna Cardoso; Doria, Rodrigo Trevisoli; CASSÉ, MIKAËL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; Pavanello, Marcelo Antonio |
| 2019 | Low temperature influence on performance and transport of Ω-Gate p-type SiGe-on-Insulator Nanowire MOSFETs | PAZ, Bruna Cardoso; CASSÉ, MIKAËL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, Marcelo A. |
| 2018 | Methodology to Separate Channel Conductions of Two Level Vertically Stacked SOI Nanowire MOSFETs | CARDOSO PAZ, BRUNA; CASSÉ, MIKAËL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; ANTONIO PAVANELLO, MARCELO |
| 2017 | Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100K | PAZ, Bruna Cardoso; CASSÉ, MIKAËL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; Pavanello, Marcelo Antonio |
| 2016 | Underestimantion of Measured Self-Heating in Nanowires By Using Gate Resistance Technique | MARINIELLO, GENARO; CASSÉ, MIKÄEL; REIMBOLD, GILLES; PAVANELLO, MARCELO |
