Browsing by Author DE SOUZA, Michelly

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Issue DateTitleAuthor(s)
2017Effect of the Back Bias on the Analog Performance of Standard FD and UTBB Transistors-Based Self-Cascode StructuresDORIA, R.T.; FLANDRE, D.; TREVISOLI, R D; DE SOUZA, Michelly; PAVANELLO, M. A.
2016Experimental and simulation analysis of electrical characteristics of common-source current mirrors implemented with asymmetric self-cascode silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistorsASSALTI, R.; D'OLIVEIRA, L. M.; PAVANELLO, M. A.; FLANDRE, Denis; DE SOUZA, Michelly
2015Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire TransistorsTREVISOLI, Renan Doria; DORIA, Rodrigo Trevisoli; DE SOUZA, Michelly; Pavanello, Marcelo Antonio
2011Junctionless Multiple-Gate Transistors for Analog ApplicationsDORIA, Rodrigo Trevisoli; YU, R.; KRANTI, Abhinav; COLINGE, J. -P.; PAVANELLO, Marcelo A.; Pavanello, Marcelo Antonio; TREVISOLI, Renan Doria; DE SOUZA, Michelly; LEE, C. W.; FERAIN, Isabelle; DEHDASHTI-AKHAVAN, N.; YAN, R.; RAZAVI, P.
2019Junctionless Nanowire Transistors Parameters Extraction Based on Drain Current MeasurementsTREVISOLI, Renan D.; DORIA, R. T.; DE SOUZA, Michelly; BARRAUD, S.; PAVANELLO, M. A.
2014Low-Frequency Noise and Effective Trap Density of Short Channel P- and N-Types Junctionless Nanowire TransistorsDORIA, Rodrigo Trevisoli; TREVISOLI, R D; DE SOUZA, Michelly; PAVANELLO, M. A.
2012Modeling of Thin-Film Lateral SOI PIN Diodes with an Alternative Multi-Branch Explicit Current ModelLUGO-MUÑOZ, D.; MUCI, Juan; ORTIZ-CONDE, Adelmo; GARCIA-SANCHEZ, Francisco; DE SOUZA, Michelly; FLANDRE, Denis; Pavanello, Marcelo Antonio
2017A New Method for Series Resistance Extraction of Nanometer MOSFETsTREVISOLI, RENAN; Pavanello, Marcelo Antonio; Doria, Rodrigo Trevisoli; DE SOUZA, Michelly; BARRAUD, SYLVAIN; VINET, MAUD; CASSE, MIKAEL; REIMBOLD, GILLES; FAYNOT, OLIVIER; GHIBAUDO, GERARD
2016On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configurationDE SOUZA, Michelly; FLANDRE, Denis; Doria, Rodrigo Trevisoli; TREVISOLI, RENAN; Pavanello, Marcelo Antonio
2018Physical Insights on the Dynamic Response of SOI n- and p-Type Junc-tionless Nanowire TransistorsDoria, Rodrigo Trevisoli; TREVISOLI, RENAN; DE SOUZA, Michelly; Pavanello, Marcelo Antonio
2013A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistorsTREVISOLI, R D; DORIA, Rodrigo Trevisoli; DE SOUZA, Michelly; PAVANELLO, Marcelo A.
2018Static and dynamic compact analytical model for junctionless nanowire transistorsPavanello, Marcelo Antonio; TREVISOLI, RENAN; DORIA, Rodrigo Trevisoli; DE SOUZA, Michelly
2008Study of Matching Properties of Graded-Channel SOI MOSFETsDE SOUZA, Michelly; FLANDRE, Denis; PAVANELLO, Marcelo A.
2014Substrate Bias Influence on the Operation of Junctionless Nanowire TransistorsTREVISOLI, Renan Doria; DORIA, Rodrigo Trevisoli; DE SOUZA, Michelly; PAVANELLO, Marcelo A.
2012Surface Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire TransistorsTREVISOLI, R D; DORIA, R. T.; DE SOUZA, Michelly; DAS, Samaresh; FERAIN, I.; PAVANELLO, Marcelo A.
2011Temperature and Silicon Film Thickness Influence on the Operation of Lateral SOI PIN Photodiodes for Detection of Short WavelengthsDE SOUZA, Michelly; BULTEEL, Olivier; FLANDRE, Denis; PAVANELLO, Marcelo A.; Pavanello, Marcelo Antonio
2014The Roles of the Gate Bias, Doping Concentration, Temperature and Geometry on the Harmonic Distortion of Junctionless Nanowire Transistors Operating in the Linear RegimeDORIA, Rodrigo Trevisoli; TREVISOLI, Renan Doria; DE SOUZA, Michelly; CUETO, Magali Estrada; CERDEIRA, Antonio; Pavanello, Marcelo Antonio
2012The Zero Temperature Coefficient in Junctionless Nanowire TransistorsTREVISOLI, Renan Doria; DORIA, Rodrigo Trevisoli; DE SOUZA, Michelly; DAS, Samaresh; FERAIN, Isabelle; PAVANELLO, Marcelo A.; Pavanello, Marcelo A.
2010Thin-Film Lateral SOI PIN Diodes for Thermal Sensing Reaching the Cryogenic RegimeDE SOUZA, Michelly; RUE, Bertrand; FLANDRE, Denis; PAVANELLO, Marcelo A.
2011Threshold voltage in junctionless nanowire transistorsTREVISOLI, Renan Doria; DORIA, Rodrigo Trevisoli; DE SOUZA, Michelly; PAVANELLO, Marcelo A.; Pavanello, Marcelo Antonio