Browsing by Author Pavanello, Marcelo Antonio

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Showing results 7 to 22 of 22 < previous 
Issue DateTitleAuthor(s)
2015Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire TransistorsTREVISOLI, Renan Doria; DORIA, Rodrigo Trevisoli; DE SOUZA, Michelly; Pavanello, Marcelo Antonio
2012Fin Cross-Section Shape Influence on Short Channel Effects of MuGETsBÜHLER, Rudolf Theoderich;BÜHLER, R. T.;Bühler, R T;BUHLER, R. T.;BÜHLER, R.;BU'HLER, RUDOLF T.;BUHLER, RUDOLF THEODERICH;BUHLER, RUDOLF T.;BUHLER, RUDOLF;T. BUHLER, RUDOLF; GIACOMINI, R. C.; Pavanello, Marcelo Antonio; PAVANELLO, Marcelo A.; Martino, João Antonio
2017Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 KPAZ, Bruna Cardoso; Doria, Rodrigo Trevisoli; CASSÉ, MIKAËL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; Pavanello, Marcelo Antonio
2016Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperaturePavanello, Marcelo Antonio; SOUZA, Michelly de; RIBEIRO, Thales Augusto; MARTINO, João Antonio; FLANDRE, D.
2011Junctionless Multiple-Gate Transistors for Analog ApplicationsDORIA, Rodrigo Trevisoli; YU, R.; KRANTI, Abhinav; COLINGE, J. -P.; PAVANELLO, Marcelo A.; Pavanello, Marcelo Antonio; TREVISOLI, Renan Doria; DE SOUZA, Michelly; LEE, C. W.; FERAIN, Isabelle; DEHDASHTI-AKHAVAN, N.; YAN, R.; RAZAVI, P.
2016Junctionless nanowire transistors operation at temperatures down to 4.2 KTREVISOLI, RENAN; SOUZA, Michelly de; DORIA, Rodrigo Trevisoli; KILCHYTSKA, V.; FLANDRE, D.; Pavanello, Marcelo Antonio
2012Modeling of Thin-Film Lateral SOI PIN Diodes with an Alternative Multi-Branch Explicit Current ModelLUGO-MUÑOZ, D.; MUCI, Juan; ORTIZ-CONDE, Adelmo; GARCIA-SANCHEZ, Francisco; DE SOUZA, Michelly; FLANDRE, Denis; Pavanello, Marcelo Antonio
2019Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistorsTREVISOLI, RENAN; Doria, Rodrigo Trevisoli; BARRAUD, SYLVAIN; Pavanello, Marcelo Antonio
2016On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configurationDE SOUZA, Michelly; FLANDRE, Denis; Doria, Rodrigo Trevisoli; TREVISOLI, RENAN; Pavanello, Marcelo Antonio
2018Physical Insights on the Dynamic Response of SOI n- and p-Type Junc-tionless Nanowire TransistorsDoria, Rodrigo Trevisoli; TREVISOLI, RENAN; DE SOUZA, Michelly; Pavanello, Marcelo Antonio
2018Static and dynamic compact analytical model for junctionless nanowire transistorsPavanello, Marcelo Antonio; TREVISOLI, RENAN; Doria, Rodrigo Trevisoli; de Souza, Michelly
2017Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100KPAZ, Bruna Cardoso; CASSÉ, MIKAËL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; Pavanello, Marcelo Antonio
2011Temperature and Silicon Film Thickness Influence on the Operation of Lateral SOI PIN Photodiodes for Detection of Short WavelengthsDE SOUZA, Michelly; BULTEEL, Olivier; FLANDRE, Denis; PAVANELLO, Marcelo A.; Pavanello, Marcelo Antonio
2014The Roles of the Gate Bias, Doping Concentration, Temperature and Geometry on the Harmonic Distortion of Junctionless Nanowire Transistors Operating in the Linear RegimeDORIA, Rodrigo Trevisoli; TREVISOLI, Renan Doria; DE SOUZA, Michelly; CUETO, Magali Estrada; CERDEIRA, Antonio; Pavanello, Marcelo Antonio
2011Threshold voltage in junctionless nanowire transistorsTREVISOLI, Renan Doria; DORIA, Rodrigo Trevisoli; DE SOUZA, Michelly; PAVANELLO, Marcelo A.; Pavanello, Marcelo Antonio
2013Trap density characterization through low-frequency noise in junctionless transistorsDORIA, R. T.; TREVISOLI, Renan Doria; DE SOUZA, Michelly; Pavanello, Marcelo Antonio
Showing results 7 to 22 of 22 < previous