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Browsing by Author DE SOUZA, Michelly
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Showing results 1 to 20 of 32
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Issue Date
Title
Author(s)
2008
Advantages of Graded-Channel SOI nMOSFETs for Application as Source-Follower Analog Buffer
DE SOUZA, Michelly
;
FLANDRE, Denis
;
PAVANELLO, Marcelo A.
2011
An explicit multi-exponential model for semiconductor junctions with series and shunt resistances
Lugo-Muñoz, Denise
;
MUCI, Juan
;
ORTIZ-CONDE, Adelmo
;
García-Sánchez, Francisco J.
;
DE SOUZA, Michelly
;
PAVANELLO, Marcelo A.
;
Pavanello, Marcelo A.
2011
Analog Operation Temperature Dependence of nMOS Junctionless Transistors Focusing on Harmonic Distortion
DORIA, Rodrigo Trevisoli
;
YU, R.
;
KRANTI, Abhinav
;
COLINGE, J. -P.
;
PAVANELLO, Marcelo A.
;
PAVANELLO, M. A.
;
TREVISOLI, Renan Doria
;
DE SOUZA, Michelly
;
LEE, C. W.
;
FERAIN, Isabelle
;
DEHDASHTI-AKHAVAN, N.
;
YAN, R.
;
RAZAVI, P.
2009
Analysis of Source Follower Buffers Implemented with Graded-Channel SOI nMOSFETs Operating at Cryogenic Temperatures
DE SOUZA, Michelly
;
FLANDRE, Denis
;
PAVANELLO, Marcelo A.
2012
Analysis of temperature variation influence on the analog performance of 45° rotated triple-gate nMuGFETs
PAVANELLO, Marcelo A.
;
DE SOUZA, Michelly
;
MARTINO, João Antonio
;
SIMOEN, Eddy
;
CLAEYS, Cor
2017
Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization
DORIA, Rodrigo Trevisoli
;
TREVISOLI, Renan D.
;
DE SOUZA, Michelly
;
VINET, MAUD
;
BARRAUD, SYLVAIN
;
PAVANELLO, Marcelo A.
2016
Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors
TREVISOLI, RENAN
;
Doria, Rodrigo Trevisoli
;
DE SOUZA, Michelly
;
BARRAUD, SYLVAIN
;
VINET, MAUD
;
Pavanello, Marcelo Antonio
2013
Approximate analytical expression for the tersminal voltage in multi-exponential diode models
ORTIZ-CONDE, Adelmo
;
GARCIA-SANCHEZ, Francisco
;
BARRIOS, Alberto Terán
;
MUCI, Juan
;
DE SOUZA, Michelly
;
Pavanello, Marcelo Antonio
2013
Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs
DE SOUZA, Michelly
;
PAZ, Bruna Cardoso
;
FLANDRE, Denis
;
Pavanello, Marcelo Antonio
2013
Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors
CERDEIRA, Antonio
;
CUETO, Magali Estrada
;
INIGUEZ, Benjamin
;
TREVISOLI, Renan Doria
;
DORIA, Rodrigo Trevisoli
;
DE SOUZA, Michelly
;
Pavanello, Marcelo Antonio
2005
A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulation
DE SOUZA, Michelly
;
PAVANELLO, Marcelo A.
;
INIGUEZ, Benjamin
;
FLANDRE, Denis
2014
Compact core model for Symmetric Double-Gate Junctionless Transistors
CERDEIRA, Antonio
;
AVILA, F.
;
INIGUEZ, Benjamin
;
DE SOUZA, Michelly
;
PAVANELLO, Marcelo A.
;
CUETO, Magali Estrada
2011
Cryogenic Operation of Junctionless Nanowire Transistor
DE SOUZA, Michelly
;
PAVANELLO, Marcelo A.
;
PAVANELLO, M. A.
;
TREVISOLI, Renan Doria
;
DORIA, Rodrigo Trevisoli
;
COLINGE, J. -P.
2017
Effect of the Back Bias on the Analog Performance of Standard FD and UTBB Transistors-Based Self-Cascode Structures
DORIA, R.T.
;
FLANDRE, D.
;
TREVISOLI, R D
;
DE SOUZA, Michelly
;
PAVANELLO, M. A.
2016
Experimental and simulation analysis of electrical characteristics of common-source current mirrors implemented with asymmetric self-cascode silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistors
ASSALTI, R.
;
D'OLIVEIRA, L. M.
;
PAVANELLO, M. A.
;
FLANDRE, Denis
;
DE SOUZA, Michelly
2015
Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors
TREVISOLI, Renan Doria
;
DORIA, Rodrigo Trevisoli
;
DE SOUZA, Michelly
;
Pavanello, Marcelo Antonio
2011
Junctionless Multiple-Gate Transistors for Analog Applications
DORIA, Rodrigo Trevisoli
;
YU, R.
;
KRANTI, Abhinav
;
COLINGE, J. -P.
;
PAVANELLO, Marcelo A.
;
Pavanello, Marcelo Antonio
;
TREVISOLI, Renan Doria
;
DE SOUZA, Michelly
;
LEE, C. W.
;
FERAIN, Isabelle
;
DEHDASHTI-AKHAVAN, N.
;
YAN, R.
;
RAZAVI, P.
2019
Junctionless Nanowire Transistors Parameters Extraction Based on Drain Current Measurements
TREVISOLI, Renan D.
;
DORIA, R. T.
;
DE SOUZA, Michelly
;
BARRAUD, S.
;
PAVANELLO, M. A.
2014
Low-Frequency Noise and Effective Trap Density of Short Channel P- and N-Types Junctionless Nanowire Transistors
DORIA, Rodrigo Trevisoli
;
TREVISOLI, R D
;
DE SOUZA, Michelly
;
PAVANELLO, M. A.
2012
Modeling of Thin-Film Lateral SOI PIN Diodes with an Alternative Multi-Branch Explicit Current Model
LUGO-MUÑOZ, D.
;
MUCI, Juan
;
ORTIZ-CONDE, Adelmo
;
GARCIA-SANCHEZ, Francisco
;
DE SOUZA, Michelly
;
FLANDRE, Denis
;
Pavanello, Marcelo Antonio