Browsing by Author FLANDRE, Denis

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Issue DateTitleAuthor(s)
20113D simulation of triple-gate MOSFETs with different mobility regionsCONDE, Jorge; CERDEIRA, Antonio; PAVANELLO, Marcelo A.; PAVANELLO, M. A.; KILCHYTSKA, V.; FLANDRE, Denis
2008Advantages of Graded-Channel SOI nMOSFETs for Application as Source-Follower Analog BufferDE SOUZA, Michelly; FLANDRE, Denis; PAVANELLO, Marcelo A.
2005Advantages of the Graded-Channel SOI FD MOSFET for Application as a Quasi-Linear ResistorCERDEIRA, Antonio; ALEMÁN, Miguel; PAVANELLO, Marcelo A.; MARTINO, João Antonio; VANCAILLIE, Laurent; FLANDRE, Denis
2000An Asymmetric Channel SOI nMOSFET for Reducing Parasitic Effects and Improving Output CharacteristicsPAVANELLO, Marcelo A.; MARTINO, João Antonio; DESSARD, V.; FLANDRE, Denis
2002Analog Circuit Design Using Graded-Channel Silicon-On-Insulator NMOSFETSPAVANELLO, Marcelo A.; MARTINO, João Antonio; FLANDRE, Denis
2000Analog Performance and Application of Graded-Channel fully depleted SOI MOSFETsPAVANELLO, Marcelo A.; MARTINO, João Antonio; DESSARD, V.; FLANDRE, Denis
2018Analysis of Mismatching on the Analog Characteristics of GC SOI MOSFETsALVES, C. R.; FLANDRE, Denis; DE SOUZA, MICHELLY
2009Analysis of Source Follower Buffers Implemented with Graded-Channel SOI nMOSFETs Operating at Cryogenic TemperaturesDE SOUZA, Michelly; FLANDRE, Denis; PAVANELLO, Marcelo A.
2013Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETsDE SOUZA, Michelly; PAZ, Bruna Cardoso; FLANDRE, Denis; Pavanello, Marcelo Antonio
2017Boosting the MOSFETs Matching by Using Diamond Layout StylePERUZZI, V. V.; Christian Renaux; FLANDRE, Denis; GIMENEZ, S. P.
2017Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature EnvironmentGALEMBECK, EGON H.S.; RENAUX, CHRISTIAN; FLANDRE, Denis; FINCO, SAULO; GIMENEZ, SALVADOR P.
2005A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulationDE SOUZA, Michelly; PAVANELLO, Marcelo A.; INIGUEZ, Benjamin; FLANDRE, Denis
2014A compact Diamond MOSFET model accounting for the PAMDLE applicable down the 150 nm nodeGIMENEZ, S. P.; Enrico Davini Neto; Vinicius Vono Peruzzi; Christian Renaux; FLANDRE, Denis
2006Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applicationsPAVANELLO, Marcelo A.; AGOPIAN, Paula Ghedini Der; MARTINO, João Antonio; FLANDRE, Denis
2015Diamond layout style impact on SOI MOSFET in high temperature environmentGimenez, Salvador Pinillos; GALEMBECK, EGON HENRIQUE SALERNO; RENAUX, CHRISTIAN; FLANDRE, Denis
2016Experimental and simulation analysis of electrical characteristics of common-source current mirrors implemented with asymmetric self-cascode silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistorsASSALTI, R.; D'OLIVEIRA, L. M.; PAVANELLO, M. A.; FLANDRE, Denis; DE SOUZA, Michelly
2006Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETSGIMENEZ, Salvador Pinillos; PAVANELLO, Marcelo A.; MARTINO, João Antonio; FLANDRE, Denis
2000Graded-Channel Fully Depleted Silicon-On-Insulator nMOSFET for Reducing the Parasitic Bipolar EffectsPAVANELLO, Marcelo A.; MARTINO, João Antonio; FLANDRE, Denis
2008Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturationDORIA, Rodrigo Trevisoli; CERDEIRA, Antonio; RASKIN, Jean Pierre; FLANDRE, Denis; PAVANELLO, Marcelo A.
2005High performance analog operation of double gate transistors with the graded-channel architecture at low temperaturesPAVANELLO, Marcelo A.; MARTINO, João Antonio; RASKIN, Jean Pierre; FLANDRE, Denis