Browsing by Author PAVANELLO, Marcelo A.

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Issue DateTitleAuthor(s)
20113D simulation of triple-gate MOSFETs with different mobility regionsCONDE, Jorge; CERDEIRA, Antonio; PAVANELLO, Marcelo A.; PAVANELLO, M. A.; KILCHYTSKA, V.; FLANDRE, Denis
2008Advantages of Graded-Channel SOI nMOSFETs for Application as Source-Follower Analog BufferDE SOUZA, Michelly; FLANDRE, Denis; PAVANELLO, Marcelo A.
2005Advantages of the Graded-Channel SOI FD MOSFET for Application as a Quasi-Linear ResistorCERDEIRA, Antonio; ALEMÁN, Miguel; PAVANELLO, Marcelo A.; MARTINO, João Antonio; VANCAILLIE, Laurent; FLANDRE, Denis
2000An Asymmetric Channel SOI nMOSFET for Reducing Parasitic Effects and Improving Output CharacteristicsPAVANELLO, Marcelo A.; MARTINO, João Antonio; DESSARD, V.; FLANDRE, Denis
2011An explicit multi-exponential model for semiconductor junctions with series and shunt resistancesLugo-Muñoz, Denise; MUCI, Juan; ORTIZ-CONDE, Adelmo; García-Sánchez, Francisco J.; DE SOUZA, Michelly; PAVANELLO, Marcelo A.; Pavanello, Marcelo A.
2002Analog Circuit Design Using Graded-Channel Silicon-On-Insulator NMOSFETSPAVANELLO, Marcelo A.; MARTINO, João Antonio; FLANDRE, Denis
2011Analog Operation Temperature Dependence of nMOS Junctionless Transistors Focusing on Harmonic DistortionDORIA, Rodrigo Trevisoli; YU, R.; KRANTI, Abhinav; COLINGE, J. -P.; PAVANELLO, Marcelo A.; PAVANELLO, M. A.; TREVISOLI, Renan Doria; DE SOUZA, Michelly; LEE, C. W.; FERAIN, Isabelle; DEHDASHTI-AKHAVAN, N.; YAN, R.; RAZAVI, P.
2000Analog Performance and Application of Graded-Channel fully depleted SOI MOSFETsPAVANELLO, Marcelo A.; MARTINO, João Antonio; DESSARD, V.; FLANDRE, Denis
2008Analog Performance of Standard and Strained Triple-Gate Silicon-On-Insulator nFINFETSPAVANELLO, Marcelo A.; MARTINO, João Antonio; SIMOEN, Eddy; ROOYACKERS, Rita; COLLAERT, Nadine; CLAEYS, Cor
2009Analysis of Source Follower Buffers Implemented with Graded-Channel SOI nMOSFETs Operating at Cryogenic TemperaturesDE SOUZA, Michelly; FLANDRE, Denis; PAVANELLO, Marcelo A.
2005Analysis of Temperature Induced Saturation Threshold Voltage Degradation in Deep-Submicrometer Ultrathin SOI MOSFETsPAVANELLO, Marcelo A.; MARTINO, João Antonio; SIMOEN, Eddy; CLAEYS, Cor
2012Analysis of temperature variation influence on the analog performance of 45° rotated triple-gate nMuGFETsPAVANELLO, Marcelo A.; DE SOUZA, Michelly; MARTINO, João Antonio; SIMOEN, Eddy; CLAEYS, Cor
2017Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterizationDORIA, Rodrigo Trevisoli; TREVISOLI, Renan D.; DE SOUZA, Michelly; VINET, MAUD; BARRAUD, SYLVAIN; PAVANELLO, Marcelo A.
2007Analysis of uniaxial and biaxial strain impact on the linearity of fully depleted SOI nMOSFETsPAVANELLO, Marcelo A.; MARTINO, João Antonio; SIMOEN, Eddy; CLAEYS, Cor
1997Analytical Modeling of the Substrate Effect on Accumulation-Mode SOI pMOSFETs at Room Temperature and at 77 KPAVANELLO, Marcelo A.; MARTINO, João Antonio; COLINGE, J. -P.
1997Analytical Modeling of the Substrate Influences on Accumulation-Mode SOI pMOSFETs at Room Temperature and at Liquid Nitrogen TemperaturePAVANELLO, Marcelo A.; MARTINO, João Antonio; COLINGE, J. -P.
2010Application of the Symmetric Doped Double-Gate Model in Circuit Simulation Containing Double-Gate Graded-Channel TransistorsCONTRERAS, Esteban; CERDEIRA, Antonio; ALVARADO, Joaquin; PAVANELLO, Marcelo A.
2018Back-Biased Undoped Nanowire-Based FETs in Silicon-On-Insulator Substrates with Nanometric ThicknessesNEMER, Juliana P.; PUYDINGER, M.; DINIZ, José Alexandre; PAVANELLO, Marcelo A.
2007Charge-Based Continuous Equations for the Transconductance and Output Conductance of Graded-Channel SOI MOSFETsDE SOUZA, Michelly; PAVANELLO, Marcelo A.
2005A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulationDE SOUZA, Michelly; PAVANELLO, Marcelo A.; INIGUEZ, Benjamin; FLANDRE, Denis
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