Please use this identifier to cite or link to this item: https://repositorio.fei.edu.br/handle/FEI/1117
Title: Drain current model for short-channel triple gate junctionless nanowire transistors
Authors: PAZ, B.C.
CASSÉ, M.
BARRAUD, S.
REIMBOLD, G.
FAYNOT, O.
ÁVILA-HERRERA, F.
CERDEIRA, A.
PAVANELLO, M.A.
Issue Date: 2016
Journal: Microelectronics and Reliability
ISSN: 0026-2714
Citation: PAZ, B.C.; CASSÉ, M.; BARRAUD, S.; REIMBOLD, G.; FAYNOT, O.; ÁVILA-HERRERA, F.; CERDEIRA, A.; PAVANELLO, M.A.. Drain current model for short-channel triple gate junctionless nanowire transistors. Microelectronics and Reliability, v. 63, n. 8, p. 1-10, 2016.
Access Type: Acesso Aberto
DOI: 10.1016/j.microrel.2016.05.006
URI: https://repositorio.fei.edu.br/handle/FEI/1117
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