Please use this identifier to cite or link to this item: https://repositorio.fei.edu.br/handle/FEI/1287
Full metadata record
DC FieldValueLanguage
dc.contributor.authorTREVISOLI, R D
dc.contributor.authorDORIA, R. T.
dc.contributor.authorDE SOUZA, M.
dc.contributor.authorDAS, S
dc.contributor.authorFERAIN, I.
dc.contributor.authorPAVANELLO, M. A.
dc.date.accessioned2019-08-19T23:45:26Z-
dc.date.available2019-08-19T23:45:26Z-
dc.date.issued2012
dc.identifier.citationTREVISOLI, R D; DORIA, R. T.; DE SOUZA, M.; DAS, S; FERAIN, I.; PAVANELLO, M. A.. Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors. IEEE Transactions on Electron Devices, v. 59, p. 3510-3518, 2012.
dc.identifier.issn0018-9383
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1287-
dc.relation.ispartofIEEE Transactions on Electron Devices
dc.rightsAcesso Aberto
dc.titleSurface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistorspt_BR
dc.typeArtigopt_BR
dc.identifier.doi10.1109/TED.2012.2219055
dc.description.volume59
dc.description.firstpage3510
dc.description.lastpage3518
Appears in Collections:Artigos

Files in This Item:
There are no files associated with this item.


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.