Please use this identifier to cite or link to this item: https://repositorio.fei.edu.br/handle/FEI/1307
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dc.contributor.authorGIMENEZ, S. P.
dc.contributor.authorGALEMBECK, E. H. S.
dc.contributor.authorRENAUX, CHRISTIAN
dc.contributor.authorFLANDRE, D
dc.date.accessioned2019-08-19T23:45:28Z-
dc.date.available2019-08-19T23:45:28Z-
dc.date.issued2015
dc.identifier.citationGIMENEZ, S. P.; GALEMBECK, E. H. S.; RENAUX, CHRISTIAN; FLANDRE, D. Impact of Using the Octagonal Layout for SOI MOSFETs in High Temperature Environment. IEEE Transactions on Device and Materials Reliability, v. 99, n. 1, p. 1-1, 2015.
dc.identifier.issn1530-4388
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1307-
dc.relation.ispartofIEEE Transactions on Device and Materials Reliability
dc.rightsAcesso Aberto
dc.titleImpact of Using the Octagonal Layout for SOI MOSFETs in High Temperature Environmentpt_BR
dc.typeArtigopt_BR
dc.identifier.doi10.1109/TDMR.2015.2474739
dc.description.volume99
dc.description.issuenumber1
dc.description.firstpage1
dc.description.lastpage1
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