Using the wave layout style to boost the digital ICs electrical performance in the radioactive environment
Nenhuma Miniatura disponível
Citações na Scopus
4
Tipo de produção
Artigo de evento
Data
2015
Autores
Navarenho-De-Souza R.
Silveira M.A.G.
Gimenez S.P.
Silveira M.A.G.
Gimenez S.P.
Orientador
Periódico
ECS Transactions
Título da Revista
ISSN da Revista
Título de Volume
Citação
NAVARENHO DE SOUZA, R.; GUAZZELI DA SILVEIRA, M.; Gimenez, S. P.. Using the Wave Layout Style to Boost the Digital ICs Electrical Performance in the Radioactive Environment. ECS Transactions (Online), v. 66, n. 5, p. 71-78, 2015.
Texto completo (DOI)
Palavras-chave
Resumo
© The Electrochemical Society.This paper presents an experimental comparative study between the Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) manufactured with the Wave ("S" gate geometry) and the standard layout (CnM) considering the Total Ionizing Dose (TID) effects and taking into account that the devices were biased during the radiation procedure to emphasize the effects. Due to the special layout characteristics and the different effects of the bird's beaks regions of the Wave MOSFET (WnM) compared to the conventional rectangular layout, this innovative layout proposal for MOSFETs is able to improve the device TID tolerance without adding cost to the Complementary MOS (CMOS) manufacturing process.