Search


Current filters:
Start a new search
Add filters:

Use filters to refine the search results.


Results 1-10 of 57 (Search time: 0.002 seconds).
Item hits:
Issue DateTitleAuthor(s)
2019Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETsPaz B.C.; Casse M.; Barraud S.; Reimbold G.; Vinet M.; Faynot O.; Pavanello M.A.
2019Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature rangePavanello M.A.; Cerdeira A.; Doria R.T.; Ribeiro T.A.; Avila-Herrera F.; Estrada M.
2019Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistorsTrevisoli R.; Doria R.T.; Barraud S.; Pavanello M.A.
2019Junctionless nanowire transistors parameters extraction based on drain current measurementsTrevisoli R.; Doria R.T.; de Souza M.; Barraud S.; Pavanello M.A.
2018Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETsPaz B.C.; Casse M.; Barraud S.; Reimbold G.; Vinet M.; Faynot O.; Pavanello M.A.
2009Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperaturesde Souza M.; Flandre D.; Pavanello M.A.
2009Trapezoidal SOI FinFET analog parameters' dependence on cross-section shapeBuhler R.T.; Giacomini R.; Pavanello M.A.; Martino J.A.
2009Cryogenic operation of FinFETs aiming at analog applicationsPavanello M.A.; Martino J.A.; Simoen E.; Claeys C.
2012Analysis of temperature variation influence on the analog performance of 45° rotated triple-gate nMuGFETsPavanello M.A.; Souza M.D.; Martino J.A.; Simoen E.; Claeys C.
2012An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devicesTrevisoli R.D.; Martino J.A.; Simoen E.; Claeys C.; Pavanello M.A.