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Issue Date	Title	Author(s)
2019	Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs	Paz B.C.; Casse M.; Barraud S.; Reimbold G.; Vinet M.; Faynot O.; Pavanello M.A.
2019	Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range	Pavanello M.A.; Cerdeira A.; Doria R.T.; Ribeiro T.A.; Avila-Herrera F.; Estrada M.
2019	Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors	Trevisoli R.; Doria R.T.; Barraud S.; Pavanello M.A.
2019	Junctionless nanowire transistors parameters extraction based on drain current measurements	Trevisoli R.; Doria R.T.; de Souza M.; Barraud S.; Pavanello M.A.
2018	Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs	Paz B.C.; Casse M.; Barraud S.; Reimbold G.; Vinet M.; Faynot O.; Pavanello M.A.
2009	Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures	de Souza M.; Flandre D.; Pavanello M.A.
2009	Trapezoidal SOI FinFET analog parameters' dependence on cross-section shape	Buhler R.T.; Giacomini R.; Pavanello M.A.; Martino J.A.
2009	Cryogenic operation of FinFETs aiming at analog applications	Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C.
2012	Analysis of temperature variation influence on the analog performance of 45° rotated triple-gate nMuGFETs	Pavanello M.A.; Souza M.D.; Martino J.A.; Simoen E.; Claeys C.
2012	An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices	Trevisoli R.D.; Martino J.A.; Simoen E.; Claeys C.; Pavanello M.A.