Desenvolvimento de nanofios transistores em substratos SOI com espessuras nanométricas
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Tipo de produção
Tese
Data
2017
Autores
Nemer, J. P.
Orientador
Pavanello, M. A.
Periódico
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Citação
NEMER, J. P. Desenvolvimento de nanofios transistores em substratos SOI com espessuras nanométricas. 2017. 133 f. Tese (Doutorado em Engenharia Elétrica) - Centro Universitário FEI, São Bernardo do Campo, 2017 Disponível em: . Acesso em: 1 ago. 2018.
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Palavras-chave
Transistor de efeito de campo de metal-óxido semicondutor
Resumo
Atualmente, uma série de trabalhos reportados na literatura mundial aponta a tecnologia Silício-sobre-Isolante (Silicon-On-Insulator SOI) como uma possível substituta da tecnologia MOS convencional na fabricação de transistores com comprimento de canal reduzido, constituindo uma importante alternativa para sustentar a contínua redução das dimensões enfrentada pela tecnologia CMOS. A utilização da tecnologia SOI apresenta melhorias tais como redução nas capacitâncias de junção e maior mobilidade dos portadores na região de canal, minimizando a ocorrência de efeitos parasitários indesejáveis que afetem o desempenho do transistor MOS. Embora o transistor na tecnologia SOI apresente diversas vantagens em comparação com a tecnologia CMOS convencional, em nosso país poucas universidades realizam a fabricação de dispositivos e circuitos em tecnologia SOI CMOS. A crescente miniaturização de dispositivos com comprimentos ainda menores, na ordem dos nanômetros, torna o processo de fabricação das junções de fonte e dreno complexo na região do canal. Devido ao comprimento de canal reduzido, as junções de fonte e dreno devem ser abruptas, de modo que a concentração de dopagem varie ordens de grandeza. Recentemente, uma estrutura de portas múltiplas foi proposta para evitar este problema: o dispositivo MOS
sem junções (Junctionless Nanowire Transistors - JNT). Estes dispositivos apresentam excelente inclinação de sublimiar, baixa corrente de fuga, e alta taxa da corrente on/off. Portanto como desafio tecnológico fabricamos transistores sem junção JNT dopados e não dopados (undoped nanowire transistor) utilizando lâmina SOI com filme de silício e óxido enterrado nanométricos. Os transistores fabricados correspondem a uma estrutura tridimensional de múltiplas portas e apresentam um processo de fabricação mais simples que o CMOS tradicional, além de diversos trabalhos na literatura o demonstrarem como uma alternativa viável para substituir os transistores planares. Esses transistores foram fabricados no Centro de Componentes Semicondutores (CCS) da Unicamp e o grande desafio foi fabricar em uma lâmina que nos proporcionava espessuras nanométricas com o laboratório que ultimamente trabalha com espessuras micrométricas. Os dois conjuntos de transistores Junctionless e um nanofio Transistor ambos ultra thin and buried oxide (UTBB), são compostos por 54 transistores com diferentes números de dedos (1, 20, 120, 640 e 1280), W (0,05µm, 0,1µm e 0,5µm) e L (1,5µm, 1µm, 0,5µm e 0,1 µm). Para estes transistores são apresentados, simulação numérica tridimensional, as etapas do processo de fabricação e caracterização elétrica dos transistores e imagens com FIB e MEV foram realizadas para caracterizar o perfil dos transistores.
Currently, a number of studies reported in the literature points to Silicon-on-Insulator technology (Silicon-On-Insulator - SOI) as an important substitute for conventional MOS technology in the manufacturing process of transistors with reduced channel length, being an important alternative to sustain continuous size reduction faced by CMOS technology. The SOI technology offers improvements such as reduced junction capacitances, higher carrier mobility in the channel region, parasitic effects reduction which affects the performance of the MOS transistor. Although the SOI technology offers several improvements, in our country few universities are manufacturing devices and circuits in SOI CMOS technology. The increasing miniaturization of devices with even smaller lengths, on the order of nanometers makes the manufacturing process of the source and drain junctions with the channel complex. Because of the reduced channel length, the source and drain junctions must be abrupt, so that the doping concentration varies several orders of magnitude in a few nanometers. Recently, a structure of multiple gates was proposed to avoid this problem: the MOS device without junctions (Junctionless Nanowire Transistors - JNT ). These devices exhibit excellent subthreshold slope, low leakage current, and a high rate of current on/off. Therefore, as a technological challenge, we fabricated doped (JNT) and undoped transistors (undoped nanowire transistor) using SOI wafer with nanometer silicon film and buried oxide. The transistors manufactured correspond to a three-dimensional structure of multiple gates and present a simpler manufacturing process than traditional CMOS, besides several works in the literature to demonstrate it as a viable alternative to replace the planar transistors. These transistors were manufactured at Unicamp's Semiconductor Components Center and the great challenge was to manufacture a wafer that provided us nanometric thicknesses with the laboratory that it works with micrometric thicknesses. The set of Junctionless transistors and one nanowire Transistor are both UTBB, are composed of 54 transistors with different number of fingers (1, 20, 120, 640 and 1280), W (0.05µm, 0.1µm and 0.5µm) and L (1.5µm, 1µm, 0.5µm and 0.1µm). For transistors are presented, three-dimensional numerical simulation, the steps of the fabrication process, electrical characterization of the transistors and images with FIB and MEV were performed to characterize the profile of the transistors.
Currently, a number of studies reported in the literature points to Silicon-on-Insulator technology (Silicon-On-Insulator - SOI) as an important substitute for conventional MOS technology in the manufacturing process of transistors with reduced channel length, being an important alternative to sustain continuous size reduction faced by CMOS technology. The SOI technology offers improvements such as reduced junction capacitances, higher carrier mobility in the channel region, parasitic effects reduction which affects the performance of the MOS transistor. Although the SOI technology offers several improvements, in our country few universities are manufacturing devices and circuits in SOI CMOS technology. The increasing miniaturization of devices with even smaller lengths, on the order of nanometers makes the manufacturing process of the source and drain junctions with the channel complex. Because of the reduced channel length, the source and drain junctions must be abrupt, so that the doping concentration varies several orders of magnitude in a few nanometers. Recently, a structure of multiple gates was proposed to avoid this problem: the MOS device without junctions (Junctionless Nanowire Transistors - JNT ). These devices exhibit excellent subthreshold slope, low leakage current, and a high rate of current on/off. Therefore, as a technological challenge, we fabricated doped (JNT) and undoped transistors (undoped nanowire transistor) using SOI wafer with nanometer silicon film and buried oxide. The transistors manufactured correspond to a three-dimensional structure of multiple gates and present a simpler manufacturing process than traditional CMOS, besides several works in the literature to demonstrate it as a viable alternative to replace the planar transistors. These transistors were manufactured at Unicamp's Semiconductor Components Center and the great challenge was to manufacture a wafer that provided us nanometric thicknesses with the laboratory that it works with micrometric thicknesses. The set of Junctionless transistors and one nanowire Transistor are both UTBB, are composed of 54 transistors with different number of fingers (1, 20, 120, 640 and 1280), W (0.05µm, 0.1µm and 0.5µm) and L (1.5µm, 1µm, 0.5µm and 0.1µm). For transistors are presented, three-dimensional numerical simulation, the steps of the fabrication process, electrical characterization of the transistors and images with FIB and MEV were performed to characterize the profile of the transistors.