Análise da mobilidade em transistores SOI de canal gradual visando simulações de circuitos
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Dissertação
Data
2020
Autores
Silva, L. M. B.
Orientador
Souza, Michelly de
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SILVA, L. M. B. Análise da mobilidade em transistores SOI de canal gradual visando simulações de circuitos. 2020. 108 f. Dissertação (Mestrado em Engenharia Elétrica) - Centro Universitário FEI, São Bernardo do Campo, 2020. Disponível em: https://doi.org/10.31414/EE.2020.D.131236.
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Transistores,Mobilidade
Resumo
de-Semiconductor Field Effect Transistor) é um transistor SOI cujo canal está dividido em duas regiões: uma região fortemente dopada e outra região fracamente dopada. A redução da concentração de dopantes na região do canal próximo ao dreno permite que os transistores GC SOI apresentem uma série de vantagens com relação ao transistor SOI convencional, uniformemente dopado, apresentando melhores características analógicas, tais como maior nível de corrente, aumento da transcondutância, redução da condutância de dreno, o que implicaem maior tensão Early, e maior tensão de ruptura. A associação destas características faz com que o GC SOI MOSFET tenha grande potencial para aplicações em circuitos integrados analógicos. Uma das etapas do projeto de circuitos integrados é a simulação destes circuitos. Para isto, é necessário que existam modelos analíticos que descrevam adequadamente os dispositivos eletrônicos. Embora exista um modelo proposto para o transistor GC SOI, este não se encontra implementado em simuladores comerciais. Desta forma, alguns trabalhos demonstram a simulação deste transistor através da associação série de dois transistores SOI uniformemente dopados com diferentes concentrações e portas curto-circuitadas. Entretanto, a
adoção desta estratégia faz com que seja necessário utilizar o dobro de transistores no circuito simulado. Adicionalmente, são inseridas as capacitâncias de fonte e dreno do ponto intermediário entre os dois transistores. Com vistas à simulação e projeto de circuitos integrados analógicos utilizando a estrutura de canal gradual, neste trabalho é apresentado um estudo da mobilidade efetiva dos transistores GC SOI. O objetivo é simular o transistor de canal gradual utilizando modelos
disponíveis em simuladores comerciais para transistores SOI uniformemente dopados, através do ajuste de seus parâmetros, que são dependentes dos comprimentos e concentrações das duas
regiões do canal. O trabalho demonstra que utilizando parâmetros de mobilidade como a mobilidade de baixo campo (µ0) e os fatores de degradação, linear (?1) e quadrático (?2), extraídos pelo método
Y-Function e realizando ajustes no parâmetro PCLM, incluso no modelo BSIM-SOI e que é relacionado ao efeito de modulação de canal, é possível reproduzir o comportamento nas curvas da corrente de dreno (IDS) e transcondutância (gm) em função da tensão de porta (VGS) e nas curvas da corrente de dreno (IDS) e condutância de saída (gD) em função da tensão de dreno(VDS) utilizando um único transistor SOI MOSFET uniformemente dopado em um simulador SPICE. Os resultados apresentaram um erro máximo de 5,26% e 10,34% nas curvas da corrente de dreno (IDS) e transcondutância (gm), respectivamente, em função da tensão de porta (VGS) para baixa tensão de dreno (VDS) em transistores GC com comprimento de canal (L) de 1 µm e 2 µm. Para alta tensão de dreno (VDS), os erros obtidos foram de 10,68% e 14,08% nas curvas da corrente de dreno e transcondutância, respectivamente, em função da tensão de porta (VGS) para transistores GC de 2 µm. As curvas da corrente de dreno(IDS) em função da tensão de dreno (VDS) apresentaram um erro menor que 5,4% com sobretensão de porta (VGT) variando de
200mV a 600mV. Foi reproduzida a condutância de saída (gD) em função da tensão de dreno (VDS), apresentando uma melhor aproximação com os dados experimentais através de ajuste no
parâmetro PCLM. Os melhores resultados foram obtidos para baixa sobretensão de porta (VGT) na região de saturação. O ajuste do parâmetro PCLM conjuntamente com os parâmetros de mobilidade, (µ0), (?1) e (?2), permitiram simular o comportamento do transistor GC com boa aproximação, o que pode tornar tal abordagem interessante para uma etapa inicial de simulação analítica de circuitos integrados analógicos utilizando o transistor GC SOI MOSFET
The GC (Graded-Channel) SOI (Silicon-On-Insulator) MOSFET (Metal-OxideSemiconductor Field Effect Transistor) transistor is a SOI transistor whose channel is divided into two regions: a highly doped region and a lightly doped region. The reduction of the doping concentration in the channel region near the drain allows GC SOI transistors to present a series of advantages over the conventional uniformly doped transistor, showing better analog characteristics, such as higher current level, increased transconductance, reduction of drain conductance, which implies higher Early voltage, and higher breakdown voltage. The association of these characteristics shows that GC SOI MOSFET has great potential for applications in analog integrated circuits. One of the steps in the design of integrated circuits is the simulation of these circuits. To allow for reliable simulations, analytical models that describe the electronic devices are required. Although a proposed model has been presented for the GC SOI transistor, it is not implemented in commercial simulators. To circumvent this, some works demonstrate the simulation of GC transistors through the association of two uniformly doped SOI transistors with different doping concentrations and short-circuited gates. However, the adoption of this strategy makes necessary to use twice as many transistors in the simulated circuit. Additionally, the use of two transistors increases the source and drain capacitances of the intermediate point between the two devices. Aiming at simulating and designing analog circuits using a graded-channel structure, this work presents a study of the effective mobility of GC SOI transistors. The objective is to simulate the graded channel transistor using available models in commercial simulators for uniformly doped SOI transistors, by adjusting its parameters, which would became dependent on the lengths and doping concentrations of the two regions of the channel. This work demonstrates that using mobility parameters such as low field mobility (µ0), linear (?1) and quadratic (?2) degradation factors, extracted by Y-Function method and making adjustments to the PCLM parameter, included in the BSIM-SOI model and which is related to the channel modulation effect, it is possible to reproduce the behavior in the drain current (IDS) and transconductance (gm) curves as a function of the gate voltage (VGS) and in the drain current (IDS) and output conductance (gD) curves as a function of drain voltage (VDS) using a single uniformly doped SOI MOSFET transistor in a SPICE simulator. The results showed a maximum error of 5.26% and 10.34% in the drain current (IDS) and transconductance (gm) curves, respectively, as a function of the gate voltage (VGS) for low drain voltage (VDS) in GC transistors with channel length (L) of 1 µm and 2 µm. For high drain voltage (VDS), the errors obtained were 10.68% and 14.08% in the drain current (IDS) and transconductance (gm) curves, respectively, as a function of the gate voltage (VGS) for 2 µm GC transistors. The drain current curves (IDS) as a function of drain voltage (VDS) showed an error of less than 5.4% with overdrive voltage (VGT) ranging from 200mV to 600mV. The output conductance (gD) as a function of the drain voltage (VDS) was reproduced, showing a better approximation with the experimental data by adjusting the PCLM parameter. The best results were obtained for low overdrive voltage (VGT) in the saturation region. The adjustment of the PCLM parameter together with the mobility parameters, (µ0), (?1) and (?2), allowed simulating the behavior of the GC transistor with good approximation, which can make this an interesting approach for an initial step of analytical simulation of analog integrated circuits using the GC SOI MOSFET transistor
The GC (Graded-Channel) SOI (Silicon-On-Insulator) MOSFET (Metal-OxideSemiconductor Field Effect Transistor) transistor is a SOI transistor whose channel is divided into two regions: a highly doped region and a lightly doped region. The reduction of the doping concentration in the channel region near the drain allows GC SOI transistors to present a series of advantages over the conventional uniformly doped transistor, showing better analog characteristics, such as higher current level, increased transconductance, reduction of drain conductance, which implies higher Early voltage, and higher breakdown voltage. The association of these characteristics shows that GC SOI MOSFET has great potential for applications in analog integrated circuits. One of the steps in the design of integrated circuits is the simulation of these circuits. To allow for reliable simulations, analytical models that describe the electronic devices are required. Although a proposed model has been presented for the GC SOI transistor, it is not implemented in commercial simulators. To circumvent this, some works demonstrate the simulation of GC transistors through the association of two uniformly doped SOI transistors with different doping concentrations and short-circuited gates. However, the adoption of this strategy makes necessary to use twice as many transistors in the simulated circuit. Additionally, the use of two transistors increases the source and drain capacitances of the intermediate point between the two devices. Aiming at simulating and designing analog circuits using a graded-channel structure, this work presents a study of the effective mobility of GC SOI transistors. The objective is to simulate the graded channel transistor using available models in commercial simulators for uniformly doped SOI transistors, by adjusting its parameters, which would became dependent on the lengths and doping concentrations of the two regions of the channel. This work demonstrates that using mobility parameters such as low field mobility (µ0), linear (?1) and quadratic (?2) degradation factors, extracted by Y-Function method and making adjustments to the PCLM parameter, included in the BSIM-SOI model and which is related to the channel modulation effect, it is possible to reproduce the behavior in the drain current (IDS) and transconductance (gm) curves as a function of the gate voltage (VGS) and in the drain current (IDS) and output conductance (gD) curves as a function of drain voltage (VDS) using a single uniformly doped SOI MOSFET transistor in a SPICE simulator. The results showed a maximum error of 5.26% and 10.34% in the drain current (IDS) and transconductance (gm) curves, respectively, as a function of the gate voltage (VGS) for low drain voltage (VDS) in GC transistors with channel length (L) of 1 µm and 2 µm. For high drain voltage (VDS), the errors obtained were 10.68% and 14.08% in the drain current (IDS) and transconductance (gm) curves, respectively, as a function of the gate voltage (VGS) for 2 µm GC transistors. The drain current curves (IDS) as a function of drain voltage (VDS) showed an error of less than 5.4% with overdrive voltage (VGT) ranging from 200mV to 600mV. The output conductance (gD) as a function of the drain voltage (VDS) was reproduced, showing a better approximation with the experimental data by adjusting the PCLM parameter. The best results were obtained for low overdrive voltage (VGT) in the saturation region. The adjustment of the PCLM parameter together with the mobility parameters, (µ0), (?1) and (?2), allowed simulating the behavior of the GC transistor with good approximation, which can make this an interesting approach for an initial step of analytical simulation of analog integrated circuits using the GC SOI MOSFET transistor