Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs
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2021-08-27
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RODRIGUES, J. C.
MARINELLO, G.
CASSE, M.
BARRAUD, S.
VINET, M.
FAYNOT, O.
Marcelo Antonio Pavanello
MARINELLO, G.
CASSE, M.
BARRAUD, S.
VINET, M.
FAYNOT, O.
Marcelo Antonio Pavanello
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SBMicro 2021 - 35th Symposium on Microelectronics Technology and Devices
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RODRIGUES, J. C.; MARINELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; PAVANELLO, M. A. Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs. SBMicro 2021 - 35th Symposium on Microelectronics Technology and Devices, Aug, 2021.
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This paper aims at analyzing the electrical characteristics of 2-level Stacked Nanowire MOSFETs at low temperatures. Fundamental device parameters such as threshold voltage, subthreshold slope and transconductance are evaluated in the temperature range of 160K to 400K. The influence of fin width variation is also studied. An analytical model of multiple-gate nanowire MOSFETs is employed to explain the experimentally observed data. It is demonstrated that the threshold voltage increases linearly with the temperature reduction. Stacked nanowires with wider fin width presents larger threshold variation with temperature. c2021 IEEE.