Influência da temperatura sobre o desempenho analógico da associação série assimétrica de transistores SOI MOS
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Dissertação
Data
2015
Autores
D'Oliveira, L. M.
Orientador
Souza, Michelly de.
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Citação
D'OLIVEIRA, L. M. Influência da temperatura sobre o desempenho analógico da associação série assimétrica de transistores SOI MOS. 2015. 123 f. Dissertação (Mestrado em Engenharia Elétrica) - Centro Universitário da FEI, São Bernardo do Campo, 2015 Disponível em: . Acesso em: 18 maio 2015.
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Palavras-chave
Temperatura,Silício,Transistor de efeito de campo de metal-óxido semicondutor
Resumo
Neste trabalho é apresentada uma análise dos efeitos da variação da temperatura sobre as características analógicas da associação série assimétrica (Asymmetric Self-Cascode – A-SC) de transistores nMOS implementados em tecnologia silício sobre isolante (Silicon-On-Insulator – SOI) totalmente depletada (Fully Depleted – FD). A A-SC é constituída por dois transistores associados em série e conectados pelas portas, onde o transistor onde é aplicada a polarização de dreno possui canal mais fracamente dopado que o outro, com a intenção de reduzir efeitos que degradam a condutância de saída. Esta estrutura combina os conceitos da associação em série simétrica (Symmetric Self-Cascode – S-SC), onde ambos transistores possuem mesma concentração de dopantes no canal, e do transistor de canal gradual (Graded Channel – GC), que consiste em um transistor único que possui regiões com diferentes concentrações de dopantes em seu canal. O estudo é realizado por meio de medidas experimentais, comparando transistores únicos, A-SC e S-SC, através da extração do ganho de tensão e da linearidade, entre outros parâmetros, para temperaturas entre 4,2 K a 500 K, com dispositivos de diversas dimensões e concentrações de dopantes. As vantagens promovidas pela estrutura A-SC em relação à S-SC e transistores únicos observadas e reportadas em temperatura ambiente são mantidas para temperaturas altas e baixas. Foi possível notar o aumento da transcondutância e a redução da condutância de dreno, resultando no aumento do ganho intrínseco de tensão. A variação dos comprimentos de canal mostra grande influência do transistor próximo à fonte sobre o comportamento final das curvas características extraídas e do ganho de tensão. Em baixas temperaturas, notou-se uma diferença de mais de 40 dB entre os ganhos de estruturas A-SC compostas por transistores de 0,75 µm e de A-SC compostas por transistores de 1 µm de comprimento de canal. Também foi observado que efeitos de degradação da condutância de dreno, como o efeito Kink, são reduzidos quanto menor a concentração de dopantes no canal dos transistores da associação. A análise do ganho de tensão em altas temperaturas mostra que a degradação da mobilidade resulta em melhor condutância de dreno, melhorando o ganho de tensão. Apesar disso, em temperaturas próximas à temperatura crítica, a transição da operação de um transistor totalmente depletado para parcialmente depletado degrada o ganho. A linearidade foi analisada neste trabalho usando as figuras de mérito a distorção harmônica referente ao segundo e terceiro harmônicos (HD2 e HD3). HD2 foi escolhida por ser aproximadamente equivalente à distorção harmônica total para os casos estudados, enquanto HD3 é a primeira harmônica ímpar, que pode ser muito influente em algumas aplicações, como circuitos balanceados. Observou-se que, em temperatura ambiente, os valores destes dois parâmetros apresentavam-se distantes um do outro, mas a temperatura baixa provocou queda de HD2. As estruturas A-SC mostram menor HD2 e HD3 que a S-SC de mesmas dimensões em todos os casos observados, mesmo com a redução da temperatura.
This work presents an analysis of the effects of temperature variation on the analog characteristics of the Asymmetric Self-Cascode (A-SC) of nMOS transistors implemented on Fully Depleted (FD) Silicon-On-Insulator technology (SOI). A-SC is composed by two transistors connected in series and with linked gates, where the channel of the transistor that has its source connected is more weakly doped than the other, with the intention of reducing effects that degrade the output conductance. This structure combines the concepts of the Symmetric Self-Cascode (S-SC), where both transistors have the same channel doping concentration, and the Graded Channel (CG), consisting of a transistor which has its channel divided in two, with the region closer to the drain lightly doped and the region closer to the source standardly doped. The study is carried out by means of experimental measurements, comparing single transistors, A-SC and S-SC, by extracting the voltage gain and harmonic distortion, among other parameters, for temperatures between 4.2 K and 500 K with devices of various dimensions and doping concentrations. The benefits promoted by the A-SC structure in comparison to the S-SC and single transistors observed and reported at room temperature are maintained through high and low temperatures. It was observed an increased transconductance and reduced the drain conductance, resulting in an increase of the intrinsic voltage gain. The variation of channel lengths shows great influence of the transistor near the source on the final behavior of the extracted characteristic curves and voltage gain. At low temperatures, there is a difference of more than 40 dB between the voltage gains of A-SC structures composed by transistors of channel lengths of 0.75 µm and composed by transistors of channel lengths of 1 µm. It was also observed that factors that impact the drain conductance degradation, such as the Kink effect, are reduced the lower the channel doping concentration of the association's transistors. The analysis of the voltage gain at high temperatures shows that the mobility degradation results in improved drain conductance, improving the voltage gain. However, in temperatures close to the critical temperature, the transition of the operation of a fully depleted transistor to partially depleted degrade the voltage gain. Linearity was analyzed in this study using the harmonic distortion referent to the second and third harmonics (HD2 and HD3) as a figure of merit. HD2 was chosen because it corresponds to approximately the total harmonic distortion for the studied cases, while HD3 is the first odd harmonic, that can be very influent in some applications, such as balanced circuits. It was observed that, at room temperature, the values of these two parameters are distant from each other, but the low-temperature drop caused HD2. The structure A-SC show lower HD2 and HD3 than S-SC of same dimensions in all cases observed, even at low temperatures.
This work presents an analysis of the effects of temperature variation on the analog characteristics of the Asymmetric Self-Cascode (A-SC) of nMOS transistors implemented on Fully Depleted (FD) Silicon-On-Insulator technology (SOI). A-SC is composed by two transistors connected in series and with linked gates, where the channel of the transistor that has its source connected is more weakly doped than the other, with the intention of reducing effects that degrade the output conductance. This structure combines the concepts of the Symmetric Self-Cascode (S-SC), where both transistors have the same channel doping concentration, and the Graded Channel (CG), consisting of a transistor which has its channel divided in two, with the region closer to the drain lightly doped and the region closer to the source standardly doped. The study is carried out by means of experimental measurements, comparing single transistors, A-SC and S-SC, by extracting the voltage gain and harmonic distortion, among other parameters, for temperatures between 4.2 K and 500 K with devices of various dimensions and doping concentrations. The benefits promoted by the A-SC structure in comparison to the S-SC and single transistors observed and reported at room temperature are maintained through high and low temperatures. It was observed an increased transconductance and reduced the drain conductance, resulting in an increase of the intrinsic voltage gain. The variation of channel lengths shows great influence of the transistor near the source on the final behavior of the extracted characteristic curves and voltage gain. At low temperatures, there is a difference of more than 40 dB between the voltage gains of A-SC structures composed by transistors of channel lengths of 0.75 µm and composed by transistors of channel lengths of 1 µm. It was also observed that factors that impact the drain conductance degradation, such as the Kink effect, are reduced the lower the channel doping concentration of the association's transistors. The analysis of the voltage gain at high temperatures shows that the mobility degradation results in improved drain conductance, improving the voltage gain. However, in temperatures close to the critical temperature, the transition of the operation of a fully depleted transistor to partially depleted degrade the voltage gain. Linearity was analyzed in this study using the harmonic distortion referent to the second and third harmonics (HD2 and HD3) as a figure of merit. HD2 was chosen because it corresponds to approximately the total harmonic distortion for the studied cases, while HD3 is the first odd harmonic, that can be very influent in some applications, such as balanced circuits. It was observed that, at room temperature, the values of these two parameters are distant from each other, but the low-temperature drop caused HD2. The structure A-SC show lower HD2 and HD3 than S-SC of same dimensions in all cases observed, even at low temperatures.