Performance of SOI Ω-Gate Nanowires from Cryogenic to High Temperatures
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2022-09-17
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Marcelo Antonio Pavanello
Michelly De Souza
Michelly De Souza
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Journal of Integrated Circuits and Systems
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PAVANELLO, M. A.; DE SOUZA, M. Performance of SOI Ω-Gate Nanowires from Cryogenic to High Temperatures. Journal of Integrated Circuits and Systems, v. 17, n. 2, p. 1-8, sept. 2022.
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© 2022, Brazilian Microelectronics Society. All rights reserved.—This review paper presents the electrical characteristics of Silicon-On-Insulator Ω-Gate nanowires in a wide range of temperatures. The operation in cryogenic and high-temperature environments will be experimentally explored. The influence of nanowire width and channel length will be dis-cussed. Nanowires with and without strain will be investigated from room temperature down to cryogenic ones, showing that strained nanowires improve carrier mobility in the whole temperature range. At high temperatures, it is demonstrated that nanowires can operate successfully up to 580 K, maintaining the ideal body factor. The effect of high temperatures on Gate-In-duced Drain Leakage will also be studied. The experimental re-sults in the whole temperature range confirm that SOI nan-owires are an excellent alternative for FinFET replacement in future technological nodes.