Asymmetric self-cascode configuration to improve the analog performance of SOI nMOS transistors
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26
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2011-10-11
Autores
Michelly De Souza
FLANDRE, D.
Marcelo Antonio Pavanello
FLANDRE, D.
Marcelo Antonio Pavanello
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Proceedings - IEEE International SOI Conference
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DE SOUZA, M.; FLANDRE, D.; PAVANELLO, M. A. Asymmetric self-cascode configuration to improve the analog performance of SOI nMOS transistors. Proceedings - IEEE International SOI Conference, Oct. 2011.
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In this work an asymmetric self-cascode (SC) structure implemented in a 150nm technology have been studied as a function of the threshold voltage and length of both transistors in the structure, aiming to improve the analog characteristics of FD SOI transistors. Experimal results indicate that this structure provided improvement in comparison to single and symmetric (SC) transistors, and that it depends on the saturation voltage of both transistors. The effect of threshold voltage and length variation of both transistors have been analyzed through 2D numerical simulations. The obtained results showed that the analog characteristics of the A-SC is improved both by reducing V T,2 and increasing L 1 and/or L 2, although there would be a maximum M 2 length in which no significant g D reduction is observed. By properly choosing these parameters, a g D reduction of more than one order of magnitude can be achieved. The A-SC has shown to provide an intrinsic voltage gain improvement of more than 20dB in comparison to single devices with similar effective channel length. © 2011 IEEE.