Drain current model for junctionless nanowire transistors
N/D
Tipo de produção
Artigo de evento
Data de publicação
2012-03-17
Texto completo (DOI)
Periódico
2012 8th International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2012
Editor
Texto completo na Scopus
Citações na Scopus
4
Autores
TREVISOLI, R. D.
Rodrido Doria
Michelly De Souza
Marcelo Antonio Pavanello
Orientadores
Resumo
Junctionless Nanowire Transistors (JNT) are considered as promising devices for sub-20 nm era due to the great scalability they provide. This work proposes a physically based analytical model for the drain current in JNTs. The proposed model is continuous from the subthreshold region to the saturation. The model is validated with 3D TCAD simulation and experimental results. © 2012 IEEE.
Citação
TREVISOLI, R. D.; DORIA, R.; DE SOUZA, M.; PAVANELLO, M. A. Drain current model for junctionless nanowire transistorsDrain current model for junctionless nanowire transistors. 2012 8th International Caribbean
Palavras-chave
Keywords
Drain Current Model; Junctionless Devices
Assuntos Scopus
Drain current models; Junctionless; Nanowire transistors; Physically based; Subthreshold region; TCAD simulation