Drain current model for junctionless nanowire transistors
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2012-03-17
Autores
TREVISOLI, R. D.
Rodrido Doria
Michelly De Souza
Marcelo Antonio Pavanello
Rodrido Doria
Michelly De Souza
Marcelo Antonio Pavanello
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Periódico
2012 8th International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2012
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TREVISOLI, R. D.; DORIA, R.; DE SOUZA, M.; PAVANELLO, M. A. Drain current model for junctionless nanowire transistorsDrain current model for junctionless nanowire transistors. 2012 8th International Caribbean
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Junctionless Nanowire Transistors (JNT) are considered as promising devices for sub-20 nm era due to the great scalability they provide. This work proposes a physically based analytical model for the drain current in JNTs. The proposed model is continuous from the subthreshold region to the saturation. The model is validated with 3D TCAD simulation and experimental results. © 2012 IEEE.