Drain current model for junctionless nanowire transistors

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dc.contributor.authorTREVISOLI, R. D.
dc.contributor.authorRodrido Doria
dc.contributor.authorMichelly De Souza
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.contributor.authorOrcidhttps://orcid.org/0000-0001-6472-4807
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-4448-4337
dc.date.accessioned2022-01-12T22:02:30Z
dc.date.available2022-01-12T22:02:30Z
dc.date.issued2012-03-17
dc.description.abstractJunctionless Nanowire Transistors (JNT) are considered as promising devices for sub-20 nm era due to the great scalability they provide. This work proposes a physically based analytical model for the drain current in JNTs. The proposed model is continuous from the subthreshold region to the saturation. The model is validated with 3D TCAD simulation and experimental results. © 2012 IEEE.
dc.identifier.citationTREVISOLI, R. D.; DORIA, R.; DE SOUZA, M.; PAVANELLO, M. A. Drain current model for junctionless nanowire transistorsDrain current model for junctionless nanowire transistors. 2012 8th International Caribbean
dc.identifier.doi10.1109/ICCDCS.2012.6188924
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4140
dc.relation.ispartof2012 8th International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2012
dc.rightsAcesso Restrito
dc.subject.otherlanguageDrain Current Model
dc.subject.otherlanguageJunctionless Devices
dc.titleDrain current model for junctionless nanowire transistors
dc.typeArtigo de evento
fei.scopus.citations4
fei.scopus.eid2-s2.0-84860998973
fei.scopus.subjectDrain current models
fei.scopus.subjectJunctionless
fei.scopus.subjectNanowire transistors
fei.scopus.subjectPhysically based
fei.scopus.subjectSubthreshold region
fei.scopus.subjectTCAD simulation
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84860998973&origin=inward
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