Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment
Citações na Scopus
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Data de publicação
GALEMBECK, E. H. S.
JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS)
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Título de Volume
GALEMBECK, E. H. S.; FLANDRE, D.; RENAUX, C.; GIMENEZ, S. P. Digital performance of OCTO layout style on SOI MOSFET at high temperature environment. JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS), v. 14, n. 2, p. 1-8, 2019.
Texto completo (DOI)
News styles layout,OCTO layout style,high temperature environment,Digital Parameters,LCE,DEPAMBRE,PAMDLE effects
This present paper performs an experimental comparative study of the main digital parameters and figures of merit of the octagonal layout style for the planar Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), named OCTO SOI MOSFETs (OSM) in comparison with the typical rectangular one at high temperature environments. The devices were manufactured with the 1 mm SOI (CMOS) technology. The results demonstrate that the OSM is capable of keeping active the Longitudinal Corner Effect (LCE), the PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivate the Parasitic MOSFETs of the Bird’s Beak Regions Effect (DEPAMBBRE) at high temperature conditions. Therefore, the OSM is able to continue to have a better electrical performance than the one found in the rectangular SOI MOSFET (RSM) counterparts, regarding the same gate areas and bias conditions. To illustrate, its on-state drain current (ION) and off-state drain current (IOFF) are respectively 186% higher and 64% smaller in relation to its RSM counterparts at high temperature conditions.