Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications

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5
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2006
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Pavanello M.A.
Der Agopian P.G.
Martino J.A.
Flandre D.
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Microelectronics Journal
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PAVANELLO, Marcelo A.; AGOPIAN, Paula Ghedini Der; MARTINO, João Antonio; FLANDRE, Denis. Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications. Microelectronics Journal, v. 37, n. 2, p. 137-144, 2006.
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We present in this work an analysis of the low temperature operation of Graded-Channel fully depleted Silicon-On-Insulator (SOI) nMOSFETs for analog applications, in the range of 100-300 K. This analysis is supported by a comparison between the results obtained by two-dimensional numerical simulations and measurements in the whole temperature range under study. The Graded-Channel transistor presents higher Early voltage if compared to the conventional fully depleted SOI nMOSFET, without degrading the transconductance over drain current, at all studied temperatures, leading to a gain larger than 20 dB compared to the conventional SOI. The resulting higher gain lies in the improvement of the electric field distribution and impact ionization rate by the graded-channel structure. © 2005 Elsevier Ltd. All reserved.
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