Electrical characterization of vertically stacked p-FET SOI nanowires

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dc.contributor.authorCardoso Paz B.
dc.contributor.authorCasse M.
dc.contributor.authorBarraud S.
dc.contributor.authorReimbold G.
dc.contributor.authorVinet M.
dc.contributor.authorFaynot O.
dc.contributor.authorAntonio Pavanello M.
dc.date.accessioned2019-08-19T23:45:13Z
dc.date.available2019-08-19T23:45:13Z
dc.date.issued2018
dc.description.abstract© 2017 Elsevier LtdThis work presents the performance and transport characteristics of vertically stacked p-type MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. The conventional procedure to extract the effective oxide thickness (EOT) and Shift and Ratio Method (S&R) have been adapted and validated through tridimensional numerical simulations. Electrical characterization is performed for NWs with [1 1 0]- and [1 0 0]-oriented channels, as a function of both fin width (WFIN) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15 nm gate length, for both orientations. Effective mobility is found around two times higher for [1 1 0]- in comparison to [1 0 0]-oriented NWs due to higher holes mobility contribution in (1 1 0) plan. Improvements obtained on ION/IOFF by reducing WFIN are mainly due to subthreshold slope decrease, once small and none mobility increase is obtained for [1 1 0]- and [1 0 0]-oriented NWs, respectively.
dc.description.firstpage84
dc.description.lastpage91
dc.description.volume141
dc.identifier.citationCARDOSO PAZ, BRUNA; CASSÉ, MIKAËL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; ANTONIO PAVANELLO, MARCELO. Electrical characterization of vertically stacked p-FET SOI nanowires. SOLID-STATE ELECTRONICS, v. 141, p. 84-91, 2018.
dc.identifier.doi10.1016/j.sse.2017.12.011
dc.identifier.issn0038-1101
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1133
dc.relation.ispartofSolid-State Electronics
dc.rightsAcesso Restrito
dc.subject.otherlanguageChannel orientation
dc.subject.otherlanguageElectrical characterization
dc.subject.otherlanguagePerformance
dc.subject.otherlanguageSOI MOSFET
dc.subject.otherlanguageTransport
dc.subject.otherlanguageVertically stacked nanowire
dc.titleElectrical characterization of vertically stacked p-FET SOI nanowires
dc.typeArtigo
fei.scopus.citations3
fei.scopus.eid2-s2.0-85041463025
fei.scopus.subjectChannel orientations
fei.scopus.subjectElectrical characterization
fei.scopus.subjectPerformance
fei.scopus.subjectSOI-MOSFETs
fei.scopus.subjectTransport
fei.scopus.updated2024-03-04
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85041463025&origin=inward
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