The role of the incomplete ionization on the operation of Junctionless Nanowire Transistors

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Rodrido Doria
Michelly De Souza
Pavanello M.A.
Proceedings - IEEE International SOI Conference
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TREVISOLI, R. D. ; DORIA, R.; DE SOUZA, M.; FERAIN, I.; DAS, S.; PAVANELLO, M. A. The role of the incomplete ionization on the operation of Junctionless Nanowire Transistors. Proceedings - IEEE International SOI Conference. Oct. 2012.
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The use of planar MOS devices for the sub-20 nm era has become a great challenge due to the loss of the gate control on the channel charges [1]. Multi-gate architecture provides a better electrostatic control, allowing a higher degree of miniaturization [1]. One of the major drawbacks of either planar or multi-gate extremely short devices is the formation of p-n junctions between source/drain and the channel, which requires precise thermal conditions in order to avoid the impurities diffusion into the channel. In this context, Junctionless Nanowire Transistors (JNTs) have been developed [2-3]. They consist of heavy doped silicon nanowires (N+ for nMOS and P+ for pMOS) surrounded by a gate stack. The device is doped from source to drain with the same element type and concentration, such that there are no gradients or junctions. Fig. 1 presents a schematic view (A) and the longitudinal section (B) of an nMOS JNT. These devices are based on bulk conduction [4] and have shown to provide better subthreshold slope, DIBL and analog properties than inversion-mode devices of similar dimensions [5-6]. Recent papers have shown the temperature (7) influence on the behavior of JNTs [7-8]. The main characteristic was the absence of the zero temperature coefficient (ZTC) bias, i.e. a point in which the drain current is almost the same independently of the temperature. In these papers, this absence has been attributed to the higher threshold voltage (Vm) and the lower mobility (μ) dependences on T [7]. This paper shows that JNTs can present a ZTC bias, which strongly depends on the series resistance. © 2012 IEEE.