Comparison between harmonic distortion in circular gate and conventional SOI NMOSFET using 0.13 μm partially-depleted SOI CMOS technology
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2007-10-12
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DANTAS, L. P.
Salvador Gimenez
Salvador Gimenez
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ECS Transactions
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DANTAS, L. P.; GIMENEZ, S. Comparison between harmonic distortion in circular gate and conventional SOI NMOSFET using 0.13 μm partially-depleted SOI CMOS technology. ECS Transactions, v. 11, n. 3, p. 85-96, Oct. 2007
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Harmonic distortion or linearity is an important merit figure for low-power, low-voltage analog integrated circuit applications. This paper studies the Harmonic Distortion in Circular Gate SOI nMOSFET, using 0.13 μm partially-depleted SOI CMOS technology for analog applications. The drain/source asymmetric effects are considered in terms of drain current as a function of the gate and drain voltages. Circular gate SOI nMOSFET harmonic distortion comparisons with conventional (rectangular gate) partially-depleted SOI nMOSFET are made, regarding the same effective channel length and width. This paper is based on experimental results. The Integral Function Method (IFM) is used to determine the total harmonic distortion (THD) and third order harmonic distortion (HD3) in order to perform this work. It is observed that circular gate devices present improved harmonic distortion as compared with rectangular gate SOI nMOSFETs, for the same effective channel length and width. © The Electrochemical Society.