Comparison between harmonic distortion in circular gate and conventional SOI NMOSFET using 0.13 μm partially-depleted SOI CMOS technology

dc.contributor.authorDANTAS, L. P.
dc.contributor.authorSalvador Gimenez
dc.date.accessioned2022-01-12T22:05:15Z
dc.date.available2022-01-12T22:05:15Z
dc.date.issued2007-10-12
dc.description.abstractHarmonic distortion or linearity is an important merit figure for low-power, low-voltage analog integrated circuit applications. This paper studies the Harmonic Distortion in Circular Gate SOI nMOSFET, using 0.13 μm partially-depleted SOI CMOS technology for analog applications. The drain/source asymmetric effects are considered in terms of drain current as a function of the gate and drain voltages. Circular gate SOI nMOSFET harmonic distortion comparisons with conventional (rectangular gate) partially-depleted SOI nMOSFET are made, regarding the same effective channel length and width. This paper is based on experimental results. The Integral Function Method (IFM) is used to determine the total harmonic distortion (THD) and third order harmonic distortion (HD3) in order to perform this work. It is observed that circular gate devices present improved harmonic distortion as compared with rectangular gate SOI nMOSFETs, for the same effective channel length and width. © The Electrochemical Society.
dc.description.firstpage85
dc.description.issuenumber3
dc.description.lastpage96
dc.description.volume11
dc.identifier.citationDANTAS, L. P.; GIMENEZ, S. Comparison between harmonic distortion in circular gate and conventional SOI NMOSFET using 0.13 μm partially-depleted SOI CMOS technology. ECS Transactions, v. 11, n. 3, p. 85-96, Oct. 2007
dc.identifier.doi10.1149/1.2778652
dc.identifier.issn1938-5862
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4326
dc.relation.ispartofECS Transactions
dc.rightsAcesso Restrito
dc.titleComparison between harmonic distortion in circular gate and conventional SOI NMOSFET using 0.13 μm partially-depleted SOI CMOS technology
dc.typeArtigo de evento
fei.scopus.citations1
fei.scopus.eid2-s2.0-45249118301
fei.scopus.subjectAnalog applications
fei.scopus.subjectAnalog integrated circuits
fei.scopus.subjectAsymmetric effects
fei.scopus.subjectDiagnostic techniques
fei.scopus.subjectDistortion (deformation)
fei.scopus.subjectDrain voltages
fei.scopus.subjectEffective channel length
fei.scopus.subjectElectrochemical Society (ECS)
fei.scopus.subjectExperimental results
fei.scopus.subjectGate devices
fei.scopus.subjectIn order
fei.scopus.subjectIntegral function method (IFM)
fei.scopus.subjectlow powers
fei.scopus.subjectLow-voltage (LV)
fei.scopus.subjectmerit figure
fei.scopus.subjectn MOSFET
fei.scopus.subjectN mosfets
fei.scopus.subjectPartially-depleted (PD)
fei.scopus.subjectSilicon-on-insulators (SOI) CMOS
fei.scopus.subjectThird-order
fei.scopus.subjectTotal Harmonic Distortion (TDH)
fei.scopus.updated2024-05-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=45249118301&origin=inward
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