Compact core model for Symmetric Double-Gate Junctionless Transistors

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Data de publicação
Cerdeira A.
Avila F.
Iniguez B.
De Souza M.
Pavanello M.A.
Estrada M.
Solid-State Electronics
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CERDEIRA, Antonio; AVILA, F.; INIGUEZ, Benjamin; DE SOUZA, Michelly; PAVANELLO, Marcelo A.; CUETO, Magali Estrada. Compact core model for Symmetric Double-Gate Junctionless Transistors. Solid-State Electronics, v. 94, p. 91-97, 2014.
Texto completo (DOI)
A new charge-based compact analytical model for Symmetric Double-Gate Junctionless Transistors is presented. The model is physically-based and considers both the depletion and accumulation operating conditions including the series resistance effects. Most model parameters are related to physical magnitudes and the extraction procedure for each of them is well established. The model provides an accurate continuous description of the transistor behavior in all operating conditions. Among important advantages with respect to previous models are the inclusion of the effect of the series resistance and the fulfilment of being symmetrical with respect to drain voltage equal to zero. It is validated with simulations for doping concentrations of 5 × 10 18 and 1 × 1019 cm-3, as well as for layer thickness of 10 and 15 nm, allowing normally-off operation. © 2014 Elsevier B.V.