Comparative study between conventional and wave planar power mosfets

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dc.contributor.authorSILVA, G. A. D.
dc.contributor.authorSalvador Gimenez
dc.contributor.authorOrcidhttps://orcid.org/0000-0002-3616-9559
dc.date.accessioned2022-04-01T06:03:09Z
dc.date.available2022-04-01T06:03:09Z
dc.date.issued2021-08-27
dc.description.abstract©2021 IEEE.One of most challenges of nanoelectronics area is to further increase the integration capacity and electrical performance of Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs). Several approaches have been done to reach this challenges, as for instance, the use of different fabrication processes, new transistors structures (bi and tridimensional), new materials etc. An alternative strategy, in which it is capable of reducing the total die area, mainly of the analog Complementary MOS (CMOS) integrated circuits (ICs), without affecting their electrical performance, is the use non-standard gate geometries (Diamond, Octo, Ellipsoidal, Fish, Wave etc.) for MOSFETs, instead of the rectangular one commonly used today. Previous studies have shown that by using Wave MOSFETs as a basic cell of the Planar Power MOSFETs (PPM) was able to reduce their total die areas. Therefore, the motivation of this paper is to verify by experimental data, the electrical behavior of PPM implemented with Wave layout style in relation to the one of PPM layouted with the conventional rectangular MOSFETs. The CMOS ICs technology used to manufacture these devices was of 350nm-ON Semiconductor. The main finding of this work is that the Wave MOSFET used as a base cell of a PPM (Wave PPM) present a similar electrical characteristics, but it is responsible to reduce in 9.7% its die area in comparison to the one found in PPM layouted with conventional MOSFETs and therefore, the Wave layout style is an alternative layout to reduce the total die area of PPM. c2021 IEEE.
dc.identifier.citationSILVA, G. A. D.; GIMENEZ, S. Comparative study between conventional and wave planar power mosfets. SBMicro 2021 - 35th Symposium on Microelectronics Technology and Devices, Aug, 2021.
dc.identifier.doi10.1109/SBMicro50945.2021.9585741
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4463
dc.relation.ispartofSBMicro 2021 - 35th Symposium on Microelectronics Technology and Devices
dc.rightsAcesso Restrito
dc.subject.otherlanguageDie area reduction
dc.subject.otherlanguagePlanar power mosfet
dc.subject.otherlanguageWave layout style
dc.titleComparative study between conventional and wave planar power mosfets
dc.typeArtigo de evento
fei.scopus.citations1
fei.scopus.eid2-s2.0-85126110254
fei.scopus.subjectArea reduction
fei.scopus.subjectComparatives studies
fei.scopus.subjectDie area
fei.scopus.subjectDie area reduction
fei.scopus.subjectElectrical performance
fei.scopus.subjectField-effect transistor
fei.scopus.subjectIntegration capacity
fei.scopus.subjectPlanar power mosfet
fei.scopus.subjectPower Mosfets
fei.scopus.subjectWave layout style
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85126110254&origin=inward
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