Analog performance of self-cascode SOI nanowires nMOSFETs aiming at low-power applications

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2018
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ASSALTI, R.
Michelly De Souza
CASSE, M.
BARRAUD, S.
REIMBOLD, G.
VINET, M.
FAYNOT, O.
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2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
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ASSALTI, R.; DE SOUZA, M.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O. Analog performance of self-cascode SOI nanowires nMOSFETs aiming at low-power applications. 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, v. 2018-March, p. 1-3, march, 2018.
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© 2017 IEEE.This paper experimentally explores the analog performance of Self-Cascode structures composed by SOI Nanowire nMOSFETs operating near the subthreshold regime. The composite structure uses transistors with distinct channel widths, biased in several back-gate voltages, to promote different threshold voltages.

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