Analog performance of self-cascode SOI nanowires nMOSFETs aiming at low-power applications
Nenhuma Miniatura disponível
Citações na Scopus
0
Tipo de produção
Artigo de evento
Data
2018
Autores
ASSALTI, R.
Michelly De Souza
CASSE, M.
BARRAUD, S.
REIMBOLD, G.
VINET, M.
FAYNOT, O.
Michelly De Souza
CASSE, M.
BARRAUD, S.
REIMBOLD, G.
VINET, M.
FAYNOT, O.
Orientador
Periódico
2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Título da Revista
ISSN da Revista
Título de Volume
Citação
ASSALTI, R.; DE SOUZA, M.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O. Analog performance of self-cascode SOI nanowires nMOSFETs aiming at low-power applications. 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, v. 2018-March, p. 1-3, march, 2018.
Texto completo (DOI)
Palavras-chave
Resumo
© 2017 IEEE.This paper experimentally explores the analog performance of Self-Cascode structures composed by SOI Nanowire nMOSFETs operating near the subthreshold regime. The composite structure uses transistors with distinct channel widths, biased in several back-gate voltages, to promote different threshold voltages.