Impact of Using the Octagonal Layout for SOI MOSFETs in a High-Temperature Environment

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dc.contributor.authorGimenez S.P.
dc.contributor.authorGalembeck E.H.S.
dc.contributor.authorRenaux C.
dc.contributor.authorFlandre D.
dc.date.accessioned2019-08-19T23:45:28Z
dc.date.available2019-08-19T23:45:28Z
dc.date.issued2015
dc.description.abstract© 2015 IEEE.The impact of high-temperature effects is experimentally investigated in the octagonal layout style for planar silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) field-effect transistors (MOSFETs), named OCTO SOI MOSFETs (OSMs), in relation to the hexagonal [diamond SOI MOSFETs (DSMs)] and the standard (rectangular conventional SOI MOSFETs) ones regarding the same bias conditions. The devices were manufactured with a 1-μ m fully depleted SOI complementary MOS (CMOS) technology. The main experimental findings demonstrate that OSM is capable of keeping active the longitudinal corner effect and the PArallel connection of MOSFET with Different channel Lengths Effect (PAMDLE) in its structure at high-temperature conditions, and consequently, it maintains its remarkably better electrical performance in comparison with the standard SOI MOSFET, mainly its capacity to reduce the leakage drain current, without causing any extra burden to the current planar SOI CMOS technology in relation to DSMs.
dc.description.firstpage626
dc.description.issuenumber4
dc.description.lastpage628
dc.description.volume15
dc.identifier.citationGIMENEZ, S. P.; GALEMBECK, E. H. S.; RENAUX, CHRISTIAN; FLANDRE, D. Impact of Using the Octagonal Layout for SOI MOSFETs in High Temperature Environment. IEEE Transactions on Device and Materials Reliability, v. 99, n. 1, p. 1-1, 2015.
dc.identifier.doi10.1109/TDMR.2015.2474739
dc.identifier.issn1558-2574
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1307
dc.relation.ispartofIEEE Transactions on Device and Materials Reliability
dc.rightsAcesso Restrito
dc.subject.otherlanguagehigh temperature environment
dc.subject.otherlanguageLCE effect and PAMDLE effect
dc.subject.otherlanguageleakage drain current
dc.subject.otherlanguageOCTO layout style
dc.titleImpact of Using the Octagonal Layout for SOI MOSFETs in a High-Temperature Environment
dc.typeArtigo
fei.scopus.citations11
fei.scopus.eid2-s2.0-84960870245
fei.scopus.subjectElectrical performance
fei.scopus.subjectHigh temperature condition
fei.scopus.subjectHigh-temperature environment
fei.scopus.subjectLCE effect and PAMDLE effect
fei.scopus.subjectMetal oxide semiconductor
fei.scopus.subjectOCTO layout style
fei.scopus.subjectParallel connections
fei.scopus.subjectSilicon-on- insulators (SOI)
fei.scopus.updated2024-03-04
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84960870245&origin=inward
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