An Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires
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Tipo de produção
Artigo de evento
Data de publicação
2022
Texto completo (DOI)
Periódico
IEEE 15th Workshop on Low Temperature Electronics, WOLTE 2022 - Conference Proceedings
Editor
Texto completo na Scopus
Citações na Scopus
1
Autores
Michelly De Souza
RODRIGUES, J. C.
MARINIELLO, G.
CASSE, M.
BARRAUD, S.
VINET, M.
FAYNOT, O.
Marcelo Antonio Pavanello
Orientadores
Resumo
© 2022 IEEE.In this work, an experimental evaluation of the gate-induced drain leakage (GIDL) of vertically stacked SOI nanowire (NW) FETs is carried out, as a function of temperature for the first time. It is shown that at room temperature, NW width decrease improves gate coupling favoring longitudinal band-to-band-tunneling, which increases normalized GIDL current. The increase of GIDL current with fin narrowing becomes more pronounced with temperature reduction. The influence of fin width has been evaluated, showing that GIDL variation with temperature depends on the device geometry.
Citação
DE SOUZA, M.; RODRIGUES, J. C.; MARINIELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; PAVANELLO, M. A. An Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires. IEEE 15th Workshop on Low Temperature Electronics, WOLTE 2022 - Conference Proceedings, jUN. 2022.
Palavras-chave
Keywords
GIDL; low temperature; SOI; stacked nanowire transistor
Assuntos Scopus
Experimental evaluation; Fin widths; Gate induced drain leakage currents; Gate induced drain leakages; Lows-temperatures; Nanowire FET; Nanowire transistors; SOI; Stacked nanowire transistor; Temperature influence