Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations
N/D
Tipo de produção
Artigo de evento
Data de publicação
2012-03/17
Texto completo (DOI)
Periódico
2012 8th International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2012
Editor
Texto completo na Scopus
Citações na Scopus
13
Autores
MARINIELLO, G.
Rodrido Doria
Michelly De Souza
Marcelo Antonio Pavanello
TREVISOLI, R. D. G.
Orientadores
Resumo
Junctionless transistors can be an excellent alternative for extremely scaled MOSFETs as they present a good behavior with no doping gradients between channel and source/drain regions. This paper aims at analyzing the gate capacitance (C gg) of junctionless transistors dependence with the three most important technological parameters for these devices: doping concentration (N D), fin width (W fin) and fin height (H fin). © 2012 IEEE.
Citação
MARINIELLO, G.; DORIA, R.; DE SOUZA, M.; PAVANELLO, M. A. ; TREVISOLI, R. D. Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations. 2012 8th International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2012. March. 2012.
Palavras-chave
Keywords
Gate Capacitance; Junctionless Devices
Assuntos Scopus
Doping concentration; Doping gradients; Fin height; Fin widths; Gate capacitance; Junctionless; MOSFETs; Source/drain regions; Technological parameters; Three dimensional device simulations