Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations
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2012-03/17
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MARINIELLO, G.
Rodrido Doria
Michelly De Souza
Marcelo Antonio Pavanello
TREVISOLI, R. D. G.
Rodrido Doria
Michelly De Souza
Marcelo Antonio Pavanello
TREVISOLI, R. D. G.
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2012 8th International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2012
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MARINIELLO, G.; DORIA, R.; DE SOUZA, M.; PAVANELLO, M. A. ; TREVISOLI, R. D. Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations. 2012 8th International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2012. March. 2012.
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Junctionless transistors can be an excellent alternative for extremely scaled MOSFETs as they present a good behavior with no doping gradients between channel and source/drain regions. This paper aims at analyzing the gate capacitance (C gg) of junctionless transistors dependence with the three most important technological parameters for these devices: doping concentration (N D), fin width (W fin) and fin height (H fin). © 2012 IEEE.