Surface-potential-based drain current analytical model for triple-gate junctionless nanowire transistors

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dc.contributor.authorTREVISOLI, R. D.
dc.contributor.authorRodrido Doria
dc.contributor.authorMichelly De Souza
dc.contributor.authorDAS, S.
dc.contributor.authorFERAIN, I.
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.contributor.authorOrcidhttps://orcid.org/0000-0001-6472-4807
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-4448-4337
dc.date.accessioned2022-01-12T22:02:52Z
dc.date.available2022-01-12T22:02:52Z
dc.date.issued2012-01-05
dc.description.abstractThis paper proposes a drain current model for triple-gate n-type junctionless nanowire transistors. The model is based on the solution of the Poisson equation. First, the 2-D Poisson equation is used to obtain the effective surface potential for long-channel devices, which is used to calculate the charge density along the channel and the drain current. The solution of the 3-D Laplace equation is added to the 2-D model in order to account for the short-channel effects. The proposed model is validated using 3-D TCAD simulations where the drain current and its derivatives, the potential, and the charge density have been compared, showing a good agreement for all parameters. Experimental data of short-channel devices down to 30 nm at different temperatures have been also used to validate the model. © 2012 IEEE.
dc.description.firstpage3510
dc.description.issuenumber12
dc.description.lastpage3518
dc.description.volume59
dc.identifier.citationTREVISOLI, R. D.; DORIA, R.; DE SOUZA, M.; PAVANELLO, M. A.; DAS, S. Surface-potential-based drain current analytical model for triple-gate junctionless nanowire transistors. IEEE Transactions on Electron Devices, v. 59, n. 12, p. 3510-3518, 2012.
dc.identifier.doi10.1109/TED.2012.2219055
dc.identifier.issn0018-9383
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4164
dc.relation.ispartofIEEE Transactions on Electron Devices
dc.rightsAcesso Restrito
dc.subject.otherlanguageDrain current model
dc.subject.otherlanguagejunctionless nanowire transistors (JNTs)
dc.subject.otherlanguageshort-channel effects (SCEs)
dc.subject.otherlanguagetemperature dependence
dc.titleSurface-potential-based drain current analytical model for triple-gate junctionless nanowire transistors
dc.typeArtigo
fei.scopus.citations93
fei.scopus.eid2-s2.0-84870302975
fei.scopus.subject2-D model
fei.scopus.subjectDrain current models
fei.scopus.subjectJunctionless
fei.scopus.subjectLong channel devices
fei.scopus.subjectNanowire transistors
fei.scopus.subjectShort-channel devices
fei.scopus.subjectShort-channel effect
fei.scopus.subjectTCAD simulation
fei.scopus.subjectTemperature dependence
fei.scopus.subjectTriple-gate
fei.scopus.updated2023-11-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84870302975&origin=inward
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