Experimental comparative analysis between junctionless and inversion mode nanowire transistors down to 10 nm-long channel lengths
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2018-10-18
Autores
Rodrigo Doria
TREVISOLI, R.
Michelly De Souza
Marcelo Antonio Pavanello
VINET, M.
CASSE, M.
FAYNOT, O.
TREVISOLI, R.
Michelly De Souza
Marcelo Antonio Pavanello
VINET, M.
CASSE, M.
FAYNOT, O.
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2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
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DORIA, R.; TREVISOLI, R.; DE SOUZA, M.; PAVANELLO, M. A.; VINET, M.; CASSE, M.; FAYNOT, O. Experimental comparative analysis between junctionless and inversion mode nanowire transistors down to 10 nm-long channel lengths. 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, p.1-3, Oct. 2018.
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This paper aims at presenting, for the first time, an experimental comparative analysis between the main electrical parameters of Junctionless (JNT) and inversion mode nanowire (IM) transistors fabricated in SOI technology down to channel length of 10 nm. The analysis has shown that JNTs present larger immunity to SCEs with respect to IM nanowires of similar dimensions. However, JNTs have shown poorer Ion than IM devices, which could be compensated through the application of multifin JNTs, at cost of increasing area consumption.