Applying the diamond layout style for FinFET

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4
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Data
2012-12-02
Autores
NETO, E. D.
Salvador Gimenez
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Periódico
ECS Transactions
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D. NETO, E.; GIMENEZ, S. Applying the diamond layout style for FinFET. ECS Transactions, v. 49, n. 1, p. 535-542, Sep. 2012
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The FinFET devices have been on focus in recent years due its elevated gate control capability over the channel region, what gives this technology a scalability advantage against others. The planar Diamond MOSFET layout, on the other hand, has also shown great results regarding its possible use on integrated circuits applications. In this paper, the concept of the Diamond layout style is extended to its three-dimensional version, the Diamond FinFET. 3D numerical simulations are performed in order to compare the possible advantages and disadvantages between this innovative layout style and its conventional counterpart, keeping the same gate area, geometric factor and bias conditions. It is shown that this new device inherits the qualities of its planar MOSFET version and it is proved that it can reduce significantly the die area of the analog and digital (mixed) low-power low-voltage integrated circuits due to its high capability as current driver. © The Electrochemical Society.

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