Applying the diamond layout style for FinFET

dc.contributor.authorNETO, E. D.
dc.contributor.authorSalvador Gimenez
dc.contributor.authorOrcidhttps://orcid.org/0000-0002-3616-9559
dc.date.accessioned2022-06-01T06:08:32Z
dc.date.available2022-06-01T06:08:32Z
dc.date.issued2012-12-02
dc.description.abstractThe FinFET devices have been on focus in recent years due its elevated gate control capability over the channel region, what gives this technology a scalability advantage against others. The planar Diamond MOSFET layout, on the other hand, has also shown great results regarding its possible use on integrated circuits applications. In this paper, the concept of the Diamond layout style is extended to its three-dimensional version, the Diamond FinFET. 3D numerical simulations are performed in order to compare the possible advantages and disadvantages between this innovative layout style and its conventional counterpart, keeping the same gate area, geometric factor and bias conditions. It is shown that this new device inherits the qualities of its planar MOSFET version and it is proved that it can reduce significantly the die area of the analog and digital (mixed) low-power low-voltage integrated circuits due to its high capability as current driver. © The Electrochemical Society.
dc.description.firstpage535
dc.description.issuenumber1
dc.description.lastpage542
dc.description.volume49
dc.identifier.citationD. NETO, E.; GIMENEZ, S. Applying the diamond layout style for FinFET. ECS Transactions, v. 49, n. 1, p. 535-542, Sep. 2012
dc.identifier.doi10.1149/04901.0535ecst
dc.identifier.issn1938-6737
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/4514
dc.relation.ispartofECS Transactions
dc.rightsAcesso Restrito
dc.titleApplying the diamond layout style for FinFET
dc.typeArtigo de evento
fei.scopus.citations6
fei.scopus.eid2-s2.0-84875819272
fei.scopus.subject3-D numerical simulation
fei.scopus.subjectBias conditions
fei.scopus.subjectChannel region
fei.scopus.subjectCurrent drivers
fei.scopus.subjectFinFET devices
fei.scopus.subjectGeometric factors
fei.scopus.subjectHigh capabilities
fei.scopus.subjectLow power Low voltages
fei.scopus.updated2025-02-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84875819272&origin=inward
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