Verilog-A Implementation of Static and Dynamic Trigate Junctionless Nanowire Transistor Compact Model
N/D
Tipo de produção
Artigo de evento
Data de publicação
2019-02-27
Texto completo (DOI)
Periódico
Latin American Electron Devices Conference, LAEDC 2019
Editor
Texto completo na Scopus
Citações na Scopus
0
Autores
MOREIRA, C. V.
TREVISOLI, R.
Marcelo Antonio Pavanello
Orientadores
Resumo
This paper presents the results of static and dynamic compact model of trigate junctionless nanowire transistor implementation in Verilog-A language to allow SPICE circuits simulations. The model implementation for n-type and p-type junctionless transistors has been compared with 3D Technology Computer-Aided Design (TCAD) simulations for several biases, doping concentrations, channel length and fin width, showing good agreement.
Citação
MOREIRA, C. V.; TREVISOLI, R.; PAVANELLO, M. A. Verilog-A Implementation of Static and Dynamic Trigate Junctionless Nanowire Transistor Compact Model. Latin American Electron Devices Conference, LAEDC 2019, Feb. 2019.
Palavras-chave
Keywords
Junctionless Transistor; SPICE; Verilog-A
Assuntos Scopus
3D technology; Channel length; Compact model; Doping concentration; Junctionless transistors; Model implementation; Nanowire transistors; Verilog-A