Verilog-A Implementation of Static and Dynamic Trigate Junctionless Nanowire Transistor Compact Model

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2019-02-27
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MOREIRA, C. V.
TREVISOLI, R.
Marcelo Antonio Pavanello
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Latin American Electron Devices Conference, LAEDC 2019
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MOREIRA, C. V.; TREVISOLI, R.; PAVANELLO, M. A. Verilog-A Implementation of Static and Dynamic Trigate Junctionless Nanowire Transistor Compact Model. Latin American Electron Devices Conference, LAEDC 2019, Feb. 2019.
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This paper presents the results of static and dynamic compact model of trigate junctionless nanowire transistor implementation in Verilog-A language to allow SPICE circuits simulations. The model implementation for n-type and p-type junctionless transistors has been compared with 3D Technology Computer-Aided Design (TCAD) simulations for several biases, doping concentrations, channel length and fin width, showing good agreement.

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