Verilog-A Implementation of Static and Dynamic Trigate Junctionless Nanowire Transistor Compact Model
dc.contributor.author | MOREIRA, C. V. | |
dc.contributor.author | TREVISOLI, R. | |
dc.contributor.author | Marcelo Antonio Pavanello | |
dc.contributor.authorOrcid | https://orcid.org/0000-0003-1361-3650 | |
dc.date.accessioned | 2022-01-12T21:56:25Z | |
dc.date.available | 2022-01-12T21:56:25Z | |
dc.date.issued | 2019-02-27 | |
dc.description.abstract | This paper presents the results of static and dynamic compact model of trigate junctionless nanowire transistor implementation in Verilog-A language to allow SPICE circuits simulations. The model implementation for n-type and p-type junctionless transistors has been compared with 3D Technology Computer-Aided Design (TCAD) simulations for several biases, doping concentrations, channel length and fin width, showing good agreement. | |
dc.identifier.citation | MOREIRA, C. V.; TREVISOLI, R.; PAVANELLO, M. A. Verilog-A Implementation of Static and Dynamic Trigate Junctionless Nanowire Transistor Compact Model. Latin American Electron Devices Conference, LAEDC 2019, Feb. 2019. | |
dc.identifier.doi | 10.1109/LAED.2019.8714741 | |
dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/3724 | |
dc.relation.ispartof | Latin American Electron Devices Conference, LAEDC 2019 | |
dc.rights | Acesso Restrito | |
dc.subject.otherlanguage | Junctionless Transistor | |
dc.subject.otherlanguage | SPICE | |
dc.subject.otherlanguage | Verilog-A | |
dc.title | Verilog-A Implementation of Static and Dynamic Trigate Junctionless Nanowire Transistor Compact Model | |
dc.type | Artigo de evento | |
fei.scopus.citations | 0 | |
fei.scopus.eid | 2-s2.0-85067195424 | |
fei.scopus.subject | 3D technology | |
fei.scopus.subject | Channel length | |
fei.scopus.subject | Compact model | |
fei.scopus.subject | Doping concentration | |
fei.scopus.subject | Junctionless transistors | |
fei.scopus.subject | Model implementation | |
fei.scopus.subject | Nanowire transistors | |
fei.scopus.subject | Verilog-A | |
fei.scopus.updated | 2024-12-01 | |
fei.scopus.url | https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85067195424&origin=inward |