Verilog-A Implementation of Static and Dynamic Trigate Junctionless Nanowire Transistor Compact Model

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dc.contributor.authorMOREIRA, C. V.
dc.contributor.authorTREVISOLI, R.
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.date.accessioned2022-01-12T21:56:25Z
dc.date.available2022-01-12T21:56:25Z
dc.date.issued2019-02-27
dc.description.abstractThis paper presents the results of static and dynamic compact model of trigate junctionless nanowire transistor implementation in Verilog-A language to allow SPICE circuits simulations. The model implementation for n-type and p-type junctionless transistors has been compared with 3D Technology Computer-Aided Design (TCAD) simulations for several biases, doping concentrations, channel length and fin width, showing good agreement.
dc.identifier.citationMOREIRA, C. V.; TREVISOLI, R.; PAVANELLO, M. A. Verilog-A Implementation of Static and Dynamic Trigate Junctionless Nanowire Transistor Compact Model. Latin American Electron Devices Conference, LAEDC 2019, Feb. 2019.
dc.identifier.doi10.1109/LAED.2019.8714741
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/3724
dc.relation.ispartofLatin American Electron Devices Conference, LAEDC 2019
dc.rightsAcesso Restrito
dc.subject.otherlanguageJunctionless Transistor
dc.subject.otherlanguageSPICE
dc.subject.otherlanguageVerilog-A
dc.titleVerilog-A Implementation of Static and Dynamic Trigate Junctionless Nanowire Transistor Compact Model
dc.typeArtigo de evento
fei.scopus.citations0
fei.scopus.eid2-s2.0-85067195424
fei.scopus.subject3D technology
fei.scopus.subjectChannel length
fei.scopus.subjectCompact model
fei.scopus.subjectDoping concentration
fei.scopus.subjectJunctionless transistors
fei.scopus.subjectModel implementation
fei.scopus.subjectNanowire transistors
fei.scopus.subjectVerilog-A
fei.scopus.updated2024-07-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85067195424&origin=inward
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