TCAD Evaluation of the Substrate Bias Influence on the Carrier Transport of Ω-Gate Nanowire MOS Transistors with Ultra-Thin BOX

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dc.contributor.authorBergamaschi F.E.
dc.contributor.authorMarcelo Antonio Pavanello
dc.contributor.authorOrcidhttps://orcid.org/0000-0003-1361-3650
dc.date.accessioned2022-01-12T21:54:04Z
dc.date.available2022-01-12T21:54:04Z
dc.date.issued2021-04-19
dc.description.abstractIn this work, the effects of substrate biasing on the electrical behavior of n-Type Ω-gate SOI nanowire MOS transistors with thin buried oxide (BOX) and variable fin width are analyzed. The analysis is carried over through 3D TCAD simulations calibrated with experimental data. Mobility degradation is observed for negative back bias due to surface-related scattering mechanisms on the front gate channel, while mobility increase is verified for positive back bias values that induce conduction in both front and back channels. High back bias values, however, which activate the back channel prior to the front one, lead to degradation in carrier mobility. On-state-off-state current ratio reduces for positive back bias due to degradation in the subthreshold slope, while DIBL is worsened due to the reduced front gate control when the substrate's positive electric field takes ahold of the inversion charges.
dc.description.firstpage1
dc.description.lastpage4
dc.identifier.citationBERGAMASCHI, F.E.; PAVANELLO, M. A. TCAD Evaluation of the Substrate Bias Influence on the Carrier Transport of Ω-Gate Nanowire MOS Transistors with Ultra-Thin BOX. LAEDC 2021 - IEEE Latin America Electron Devices Conference, p. 1-4, Apr. 2021.
dc.identifier.doi10.1109/LAEDC51812.2021.9437923
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/3580
dc.relation.ispartofLAEDC 2021 - IEEE Latin America Electron Devices Conference
dc.rightsAcesso Restrito
dc.subject.otherlanguageMobility
dc.subject.otherlanguageNanowire MOS transistors
dc.subject.otherlanguageSubstrate bias
dc.subject.otherlanguageThin BOX
dc.titleTCAD Evaluation of the Substrate Bias Influence on the Carrier Transport of Ω-Gate Nanowire MOS Transistors with Ultra-Thin BOX
dc.typeArtigo de evento
fei.scopus.citations2
fei.scopus.eid2-s2.0-85108192433
fei.scopus.subjectElectrical behaviors
fei.scopus.subjectMobility degradation
fei.scopus.subjectOff-state current
fei.scopus.subjectScattering mechanisms
fei.scopus.subjectSubstrate biasing
fei.scopus.subjectSubthreshold slope
fei.scopus.subjectThin buried oxide (BOX)
fei.scopus.subjectUltra-thin boxes
fei.scopus.updated2024-08-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85108192433&origin=inward
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