Analog performance of n-and p-FET SOI nanowires including channel length and temperature influence
Nenhuma Miniatura disponível
Citações na Scopus
8
Tipo de produção
Artigo de evento
Data
2016-01-27
Autores
PAZ, B. C.
Marcelo Antonio Pavanello
CASSE, M.
BARRAUD, S.
REIMBOLD, G.
VINET, M.
FAYNOT, O.
Marcelo Antonio Pavanello
CASSE, M.
BARRAUD, S.
REIMBOLD, G.
VINET, M.
FAYNOT, O.
Orientador
Periódico
2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2016
Título da Revista
ISSN da Revista
Título de Volume
Citação
PAZ, B. C.; PAVANELLO, M. A.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O. Analog performance of n-and p-FET SOI nanowires including channel length and temperature influence. 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2016, p. 170-173, Jan. 2016.
Texto completo (DOI)
Palavras-chave
Resumo
This work aims to present the analog performance of silicon n-Type and p-MOSFET SOI nanowires. Analog parameters are shown at room temperature for both n-and p-Type, long and short channel devices with different channel width. Results for long channel n-MOS nanowires are investigated for the first time for low temperatures down to 100K. Moreover, an analysis is shown comparing the intrinsic voltage gain in nanowires and quasi-planar transistors. The mobility dependence on the temperature is found to be the key parameter to describe the behavior of both transconductance and output conductance when decreasing temperature.