Analytical modeling of double gate graded-channel SOI transistors for analog applications
N/D
Tipo de produção
Artigo de evento
Data de publicação
2009-05-29
Texto completo (DOI)
Periódico
ECS Transactions
Editor
Texto completo na Scopus
Citações na Scopus
0
Autores
FERREIRA, F. A. L. P.
CERDEIRA, A.
FLANDRE, D.
Marcelo Antonio Pavanello
Orientadores
Resumo
In this work we present the development of an analytical model for double gate (DG) Silicon-on-Insulator (SOI) nMOSFET transistor with graded-channel (GC), valid from weak inversion to strong inversion. Atlas numerical two-dimensional simulations and experimental results are used to validate the proposed model. Good agreement between simulated, modeled and experimental results is demonstrated. ©The Electrochemical Society.
Citação
FERREIRA, F. A. L. P.; CERDEIRA, A.; FLANDRE, D.; PAVANELLO, M. A. Analytical modeling of double gate graded-channel SOI transistors for analog applications. ECS Transactions, v. 19, n. 4, p. 139-144, May, 2009.
Palavras-chave
Keywords
Assuntos Scopus
Analog applications; Analytical model; Analytical modeling; Double gate; nMOSFET transistors; Silicon-on-insulators; SOI transistors; Strong inversion; Two-dimensional simulations; Weak inversions