Dependence of the optimum length of light doped region of GC SOI nMOSFET with front gate bias
dc.contributor.author | ASSALTI, R. | |
dc.contributor.author | Marcelo Antonio Pavanello | |
dc.contributor.author | FLANDRE, D. | |
dc.contributor.author | Michelly De Souza | |
dc.contributor.authorOrcid | https://orcid.org/0000-0003-1361-3650 | |
dc.contributor.authorOrcid | https://orcid.org/0000-0001-6472-4807 | |
dc.date.accessioned | 2022-01-12T22:00:33Z | |
dc.date.available | 2022-01-12T22:00:33Z | |
dc.date.issued | 2014-10-29 | |
dc.description.abstract | This work assesses the analog performance of Graded-Channel FD SOI nMOSFET transistors regarding the dependence of gate voltage overdrive over the length of lightly doped region which maximizes the intrinsic voltage gain, unit gain frequency and breakdown voltage. It is shown that the optimum length of lightly doped region depends on the target application of GC devices. | |
dc.identifier.citation | ASSALTI, R.; PAVANELLO, M. A.; FLANDRE, D.; DE SOUZA, M. Dependence of the optimum length of light doped region of GC SOI nMOSFET with front gate bias. 2014 29th Symposium on Microelectronics Technology and Devices: Chip in Aracaju, SBMicro 2014, Oct, 2014. | |
dc.identifier.doi | 10.1109/SBMicro.2014.6940099 | |
dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/4007 | |
dc.relation.ispartof | 2014 29th Symposium on Microelectronics Technology and Devices: Chip in Aracaju, SBMicro 2014 | |
dc.rights | Acesso Restrito | |
dc.subject.otherlanguage | Breakdown voltage | |
dc.subject.otherlanguage | Gate voltage overdrive | |
dc.subject.otherlanguage | Graded-Channel | |
dc.subject.otherlanguage | Intrinsic voltage gain | |
dc.subject.otherlanguage | Unit gain frequency | |
dc.title | Dependence of the optimum length of light doped region of GC SOI nMOSFET with front gate bias | |
dc.type | Artigo de evento | |
fei.scopus.citations | 0 | |
fei.scopus.eid | 2-s2.0-84912068479 | |
fei.scopus.subject | Analog performance | |
fei.scopus.subject | Gain frequencies | |
fei.scopus.subject | Gate voltages | |
fei.scopus.subject | Graded channels | |
fei.scopus.subject | Intrinsic voltage gains | |
fei.scopus.subject | nMOSFET transistors | |
fei.scopus.subject | Optimum length | |
fei.scopus.subject | Target application | |
fei.scopus.updated | 2025-01-01 | |
fei.scopus.url | https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84912068479&origin=inward |