A novel asynchronous interface with pausible clock for partitioned synchronous modules

Abstract

© 2015 IEEE.Contemporary digital systems must necessarily be based on the 'System-on-Chip - SoC' concept. An interesting style for SoC design is GALS (Globally Asynchronous, Locally Synchronous) paradigm. Currently, the major drawback in the design of a GALS system shows to be the asynchronous interface (asynchronous wrapper - AW), especially when the GALS system is applied to a multi-point topology. The AW interfaces found in literature are always based on controller ports. They are responsible for data communication between locally synchronous modules, where to each point of data communication there is an input or output port. The increasing number of port leads to complex AWs and to a high increase in area. This paper proposes a new asynchronous GALS interface focused on multi-point GALS. For a case study considering a multi-point data communication system, the proposed interface achieved an average reduction in area (products + literals) of 85% and 74%, when compared to two different AWs found in literature.