Modeling of silicon stacked nanowire and nanosheet transistors at high temperatures
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Tipo de produção
Artigo de evento
Data de publicação
2022-07-04
Texto completo (DOI)
Periódico
2022 IEEE Latin America Electron Devices Conference, LAEDC 2022
Editor
Texto completo na Scopus
Citações na Scopus
1
Autores
CERDEIRA, A.
ESTRADA, M.
DA SILVA, G. M.
RODRIGUES, J. C.
Marcelo Antonio Pavanello
Orientadores
Resumo
© 2022 IEEE.In this work, we demonstrate that the Symmetric Doped Double-Gate Model (SDDGM), previously validated for modeling FinFETs, stacked nanowire, and nanosheet transistors at room temperature, can be extended for modeling stacked nanowire and nanosheet transistors at high temperatures. The modeled results are validated by comparison with experimental data.
Citação
CERDEIRA, A.; ESTRADA, M.; DA SILVA, G. M.; RODRIGUES, J. C.; PAVANELLO, M. A. Modeling of silicon stacked nanowire and nanosheet transistors at high temperatures. 2022 IEEE Latin America Electron Devices Conference, LAEDC 2022, Jul. 2022.
Palavras-chave
Keywords
compact modeling; high temperature; Si nanosheets; stacked transistors
Assuntos Scopus
Compact model; Double-gate; FinFETs; Gate models; Highest temperature; Si nanosheet; Stacked transistors; Symmetrics