Analysis of COTS FPGA SEU-sensitivity to combined effects of conducted-EMI and TID

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dc.contributor.authorVILLA, P.
dc.contributor.authorBEZERRA, E.
dc.contributor.authorGOERL, R.
dc.contributor.authorPOEHLS, L.
dc.contributor.authorVARGA, F.
dc.contributor.authorMEDINA N.
dc.contributor.authorADDED, N.
dc.contributor.authorDE AGUIAR, V.
dc.contributor.authorMACCHIORE, E.
dc.contributor.authorAGUIRRE, F.
dc.contributor.authorMarcilei Aparecida Guazzelli
dc.contributor.authorOrcidhttps://orcid.org/0000-0001-7110-7241
dc.date.accessioned2022-01-12T21:58:02Z
dc.date.available2022-01-12T21:58:02Z
dc.date.issued2017-07-31
dc.description.abstract© 2017 IEEE.The desirable use of Field-Programmable Gate Arrays (FGPAs) in aerospace & defense field has become a general consensus among IC and embedded system designers. Radiation-hardened (rad-hard) electronics used in this domain is regulated under severe and complex political and commercial treaties. In order to refrain from these undesired political and commercial barriers component-off-the-shelf (COTS) FPGAs (despite the fact of their low reliability) have been considered as a promising alternative to replace rad-hard ICs. In this scenario, this paper analyses the Single-Event Upset (SEU) sensitivity of the Microsemi ProASIC3E A3PE1500 COTS FPGA for a combined set of Electromagnetic Interference (EMI) and Total-Ionizing Dose (TID) tests. This component is under pre-qualification process for use in some satellites of the Brazilian Space Program. Experimental results are herein briefly presented and discussed. These results allow us to consider this component as a strong candidate to replace rad-hard FPGAs, if its use is combined with strict system-level fault-tolerant strategies for error detection and correction (EDAC).
dc.description.firstpage27
dc.description.lastpage32
dc.identifier.citationVILLA, P.; BEZERRA, E.; GOERL, R.; POEHLS, L.; VARGA, F.; MEDINA N.; ADDED, N.; DE AGUIAR, V.; MACCHIORE, E.; AGUIRRE, F.; GUAZZELLI, M. A. Analysis of COTS FPGA SEU-sensitivity to combined effects of conducted-EMI and TID. Proceedings of the 2017 11th International Workshop on the Electromagnetic Compatibility of Integrated Circuits, EMCCompo 2017, p. 27-32, jul. 2017.
dc.identifier.doi10.1109/EMCCompo.2017.7998076
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/3834
dc.relation.ispartofProceedings of the 2017 11th International Workshop on the Electromagnetic Compatibility of Integrated Circuits, EMCCompo 2017
dc.rightsAcesso Restrito
dc.subject.otherlanguageCombined Qualification Test for EMI
dc.subject.otherlanguageCOTS
dc.subject.otherlanguageFPGA
dc.subject.otherlanguageMicrosemi ProAsic3E
dc.subject.otherlanguageSEU and TID
dc.subject.otherlanguageSEU Sensitivity
dc.titleAnalysis of COTS FPGA SEU-sensitivity to combined effects of conducted-EMI and TID
dc.typeArtigo de evento
fei.scopus.citations5
fei.scopus.eid2-s2.0-85028510359
fei.scopus.subjectCOTS
fei.scopus.subjectMicrosemi ProAsic3E
fei.scopus.subjectQualification test
fei.scopus.subjectSEU and TID
fei.scopus.subjectSEU Sensitivity
fei.scopus.updated2024-05-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85028510359&origin=inward
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