An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models

dc.contributor.authorPereira A.S.N.
dc.contributor.authorde Streel G.
dc.contributor.authorPlanes N.
dc.contributor.authorHaond M.
dc.contributor.authorGiacomini R.
dc.contributor.authorFlandre D.
dc.contributor.authorKilchytska V.
dc.date.accessioned2019-08-19T23:45:14Z
dc.date.available2019-08-19T23:45:14Z
dc.date.issued2017
dc.description.abstract© 2016 Elsevier LtdThe Drain Induced Barrier Lowering (DIBL) behavior in Ultra-Thin Body and Buried oxide (UTBB) transistors is investigated in details in the temperature range up to 150 °C, for the first time to the best of our knowledge. The analysis is based on experimental data, physical device simulation, compact model (SPICE) simulation and previously published models. Contrary to MASTAR prediction, experiments reveal DIBL increase with temperature. Physical device simulations of different thin-film fully-depleted (FD) devices outline the generality of such behavior. SPICE simulations, with UTSOI DK2.4 model, only partially adhere to experimental trends. Several analytic models available in the literature are assessed for DIBL vs. temperature prediction. Although being the closest to experiments, Fasarakis’ model overestimates DIBL(T) dependence for shortest devices and underestimates it for upsized gate lengths frequently used in ultra-low-voltage (ULV) applications. This model is improved in our work, by introducing a temperature-dependent inversion charge at threshold. The improved model shows very good agreement with experimental data, with high gain in precision for the gate lengths under test.
dc.description.firstpage67
dc.description.issuenumber1
dc.description.lastpage71
dc.description.volume128
dc.identifier.citationPEREIRA, A. S. N.; STREEL, G.; PLANES, N.; HAOND, M.; GIACOMINI, R.; FLANDRE, D.; KILCHYTSKA, V.. An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models. Solid-State Electronics, v. 128, n. 1, p. 67-71, 2017.
dc.identifier.doi10.1016/j.sse.2016.10.017
dc.identifier.issn0038-1101
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1152
dc.relation.ispartofSolid-State Electronics
dc.rightsAcesso Restrito
dc.subject.otherlanguageDIBL
dc.subject.otherlanguageFully-Depleted Silicon-On-Insulator (FD SOI)
dc.subject.otherlanguageTemperature dependence
dc.subject.otherlanguageUTBB
dc.titleAn in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models
dc.typeArtigo
fei.scopus.citations2
fei.scopus.eid2-s2.0-85005982593
fei.scopus.subjectDIBL
fei.scopus.subjectDrain-induced barrier lowering
fei.scopus.subjectFully depleted devices
fei.scopus.subjectFully depleted silicon on insulators (FD SOI)
fei.scopus.subjectTemperature dependence
fei.scopus.subjectTemperature dependent
fei.scopus.subjectTemperature prediction
fei.scopus.subjectUTBB
fei.scopus.updated2024-02-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85005982593&origin=inward
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