Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

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dc.contributor.authorPavanello M.A.
dc.contributor.authorMartino J.A.
dc.contributor.authorSimoen E.
dc.contributor.authorRooyackers R.
dc.contributor.authorCollaert N.
dc.contributor.authorClaeys C.
dc.date.accessioned2019-08-19T23:45:09Z
dc.date.available2019-08-19T23:45:09Z
dc.date.issued2008
dc.description.abstractThis work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-κ dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. © 2008 Elsevier Ltd. All rights reserved.
dc.description.firstpage1904
dc.description.issuenumber12
dc.description.lastpage1909
dc.description.volume52
dc.identifier.citationPAVANELLO, Marcelo A.; MARTINO, João Antonio; SIMOEN, Eddy; ROOYACKERS, Rita; COLLAERT, Nadine; CLAEYS, Cor. Analog Performance of Standard and Strained Triple-Gate Silicon-On-Insulator nFINFETS. Solid-State Electronics, v. 52, n. 12, p. 1904-1909, 2008.
dc.identifier.doi10.1016/j.sse.2008.06.049
dc.identifier.issn0038-1101
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1072
dc.relation.ispartofSolid-State Electronics
dc.rightsAcesso Restrito
dc.subject.otherlanguageAnalog operation
dc.subject.otherlanguageBiaxial strain
dc.subject.otherlanguageEarly voltage
dc.subject.otherlanguageFinFET
dc.subject.otherlanguageIntrinsic gain
dc.subject.otherlanguageTriple-gate
dc.titleAnalog performance of standard and strained triple-gate silicon-on-insulator nFinFETs
dc.typeArtigo
fei.scopus.citations18
fei.scopus.eid2-s2.0-56049090995
fei.scopus.subjectAnalog operation
fei.scopus.subjectBiaxial strain
fei.scopus.subjectEarly voltage
fei.scopus.subjectFinFET
fei.scopus.subjectIntrinsic gain
fei.scopus.subjectTriple-gate
fei.scopus.updated2024-03-04
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=56049090995&origin=inward
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