Impact of the octagonal layout style for MOSFETs using 180nm Bulk CMOS ICs technology node
Nenhuma Miniatura disponível
Citações na Scopus
2
Tipo de produção
Artigo de evento
Data
2018-Aug-31
Autores
LOESCH, D. S.
Salvador Gimenez
SWART, J. W.
Marcilei Aparecida Guazzelli
Salvador Gimenez
SWART, J. W.
Marcilei Aparecida Guazzelli
Orientador
Periódico
33rd Symposium on Microelectronics Technology and Devices, SBMicro 2018
Título da Revista
ISSN da Revista
Título de Volume
Citação
LOESCH, D. S.; GIMENEZ, S.; SWART, J. W.; GUAZZELLI, M. A. Impact of the octagonal layout style for MOSFETs using 180nm Bulk CMOS ICs technology node. 33rd Symposium on Microelectronics Technology and Devices, SBMicro 2018, Aug. 2018.
Texto completo (DOI)
Palavras-chave
Resumo
This paper aims to evaluate the impact of the octagonal layout style for MOSFETs regarding the 180nm Bulk CMOS ICs technology node. The main results of this study show that the nMOSFETs with octagonal gate geometries are capable of improving the drain current, Early voltage, intrinsic voltage gain, and on-state drain to source resistance about 150%, 800%, 66% and 50%, respectively, in relation to the standard rectangular MOSFET counterparts, regarding the same bias conditions. Therefore, the LCE and PAMDLE effects continue being actives regarding this 180 nm Bulk CMOS ICs technology node.