Impact of the octagonal layout style for MOSFETs using 180nm Bulk CMOS ICs technology node

Página do item simplificado
dc.contributor.authorLOESCH, D. S.
dc.contributor.authorSalvador Gimenez
dc.contributor.authorSWART, J. W.
dc.contributor.authorMarcilei Aparecida Guazzelli
dc.contributor.authorOrcidhttps://orcid.org/0000-0002-3616-9559
dc.contributor.authorOrcidhttps://orcid.org/0000-0001-7110-7241
dc.date.accessioned2022-01-12T21:57:01Z
dc.date.available2022-01-12T21:57:01Z
dc.date.issued2018-Aug-31
dc.description.abstractThis paper aims to evaluate the impact of the octagonal layout style for MOSFETs regarding the 180nm Bulk CMOS ICs technology node. The main results of this study show that the nMOSFETs with octagonal gate geometries are capable of improving the drain current, Early voltage, intrinsic voltage gain, and on-state drain to source resistance about 150%, 800%, 66% and 50%, respectively, in relation to the standard rectangular MOSFET counterparts, regarding the same bias conditions. Therefore, the LCE and PAMDLE effects continue being actives regarding this 180 nm Bulk CMOS ICs technology node.
dc.identifier.citationLOESCH, D. S.; GIMENEZ, S.; SWART, J. W.; GUAZZELLI, M. A. Impact of the octagonal layout style for MOSFETs using 180nm Bulk CMOS ICs technology node. 33rd Symposium on Microelectronics Technology and Devices, SBMicro 2018, Aug. 2018.
dc.identifier.doi10.1109/SBMicro.2018.8511476
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/3764
dc.relation.ispartof33rd Symposium on Microelectronics Technology and Devices, SBMicro 2018
dc.rightsAcesso Restrito
dc.subject.otherlanguageElectrical characterization
dc.subject.otherlanguageLCE
dc.subject.otherlanguageOctagonal layout style
dc.subject.otherlanguageOCTO MOSFET
dc.subject.otherlanguagePAMDLE
dc.titleImpact of the octagonal layout style for MOSFETs using 180nm Bulk CMOS ICs technology node
dc.typeArtigo de evento
fei.scopus.citations2
fei.scopus.eid2-s2.0-85057423084
fei.scopus.subjectBias conditions
fei.scopus.subjectElectrical characterization
fei.scopus.subjectIntrinsic voltage gains
fei.scopus.subjectMOS-FET
fei.scopus.subjectOctagonal layout style
fei.scopus.subjectPAMDLE
fei.scopus.subjectSource resistance
fei.scopus.subjectTechnology nodes
fei.scopus.updated2024-08-01
fei.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85057423084&origin=inward
Arquivos
Coleções
Artigos