Analytical compact model for triple gate junctionless MOSFETs
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2015-10-13
Autores
HERRERA, F. A.
CERDEIRA, A.
PAZ, B. C.
ESTRADA, M.
Marcelo Antonio Pavanello
CERDEIRA, A.
PAZ, B. C.
ESTRADA, M.
Marcelo Antonio Pavanello
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SBMicro 2015 - 30th Symposium on Microelectronics Technology and Devices
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https://orcid.org/0000-0003-1361-3650
HERRERA, F. A.; CERDEIRA, A.; PAZ, B. C.; ESTRADA, M.; PAVANELLO, M. A. Analytical compact model for triple gate junctionless MOSFETs. SBMicro 2015 - 30th Symposium on Microelectronics Technology and Devices. Oct. 2015.
HERRERA, F. A.; CERDEIRA, A.; PAZ, B. C.; ESTRADA, M.; PAVANELLO, M. A. Analytical compact model for triple gate junctionless MOSFETs. SBMicro 2015 - 30th Symposium on Microelectronics Technology and Devices. Oct. 2015.
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A new compact analytical model for triple gate junctionless transistors JLT is presented considering the capacitances when the fin height is reduced. For its calculation, the capacitance is separated into gate and silicon height capacitance. On the modeling side, threshold voltage, drain current model and short channel effects are modeled considering the influence of variable fin height. Based on our previous developed analytical model for 2D devices, which neglects the fin height effects, a 3D analytical compact model was developed including short channel effects. The 3D model presented is useful for modeling silicon triple gate junctionless transistors. The model validation is done by simulations varying the fin height and channel length.